commit 525ce914edf136d2bd02ac8c404d56c52e737f4d
author Christopher Ferris <cferris@google.com> Wed Jul 26 13:12:53 2017 -0700
committer Christopher Ferris <cferris@google.com> Thu Jul 27 16:01:39 2017 -0700
tree 0da29892c385ef568bc67ff2f2814bfb2f7b0412
parent 4f36cabd8d1b1f3ed6ad4586f86aad5731f4bdaf

Update to kernel headers v4.12.3.

Test: Built angler.
Change-Id: Icbcf4fac2334de8409b049ed7a3b4c24b4e98ce9

libc/kernel/uapi/rdma/mlx5-abi.h

diff --git a/libc/kernel/uapi/rdma/mlx5-abi.h b/libc/kernel/uapi/rdma/mlx5-abi.h
index 1a8eb0d..6e76a3d 100644
--- a/libc/kernel/uapi/rdma/mlx5-abi.h
+++ b/libc/kernel/uapi/rdma/mlx5-abi.h
@@ -19,6 +19,7 @@
 #ifndef MLX5_ABI_USER_H
 #define MLX5_ABI_USER_H
 #include <linux/types.h>
+#include <linux/if_ether.h>
 enum {
   MLX5_QP_FLAG_SIGNATURE = 1 << 0,
   MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
@@ -31,18 +32,22 @@
 };
 #define MLX5_IB_UVERBS_ABI_VERSION 1
 struct mlx5_ib_alloc_ucontext_req {
-  __u32 total_num_uuars;
-  __u32 num_low_latency_uuars;
+  __u32 total_num_bfregs;
+  __u32 num_low_latency_bfregs;
+};
+enum mlx5_lib_caps {
+  MLX5_LIB_CAP_4K_UAR = (__u64) 1 << 0,
 };
 struct mlx5_ib_alloc_ucontext_req_v2 {
-  __u32 total_num_uuars;
-  __u32 num_low_latency_uuars;
+  __u32 total_num_bfregs;
+  __u32 num_low_latency_bfregs;
   __u32 flags;
   __u32 comp_mask;
   __u8 max_cqe_version;
   __u8 reserved0;
   __u16 reserved1;
   __u32 reserved2;
+  __u64 lib_caps;
 };
 enum mlx5_ib_alloc_ucontext_resp_mask {
   MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
@@ -51,10 +56,17 @@
   MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
   MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
 };
+enum mlx5_user_inline_mode {
+  MLX5_USER_INLINE_MODE_NA,
+  MLX5_USER_INLINE_MODE_NONE,
+  MLX5_USER_INLINE_MODE_L2,
+  MLX5_USER_INLINE_MODE_IP,
+  MLX5_USER_INLINE_MODE_TCP_UDP,
+};
 struct mlx5_ib_alloc_ucontext_resp {
   __u32 qp_tab_size;
   __u32 bf_reg_size;
-  __u32 tot_uuars;
+  __u32 tot_bfregs;
   __u32 cache_line_size;
   __u16 max_sq_desc_sz;
   __u16 max_rq_desc_sz;
@@ -67,8 +79,11 @@
   __u32 response_length;
   __u8 cqe_version;
   __u8 cmds_supp_uhw;
-  __u16 reserved2;
+  __u8 eth_min_inline;
+  __u8 reserved2;
   __u64 hca_core_clock_offset;
+  __u32 log_uar_size;
+  __u32 num_uars_per_page;
 };
 struct mlx5_ib_alloc_pd_resp {
   __u32 pdn;
@@ -171,7 +186,7 @@
   __u32 reserved1;
 };
 struct mlx5_ib_create_qp_resp {
-  __u32 uuar_index;
+  __u32 bfreg_index;
 };
 struct mlx5_ib_alloc_mw {
   __u32 comp_mask;