implement work around for tegra errata 657451

tegra 2 processors have a bug in the register read path of bit 20 of
the CP15 c13, 3 register (used for software thread local storage)

the kernel work-around for this bug is to mux the value from bit 20
into bit 0; since the TLS value used by Android is an aligned address,
bit 0 is known to be available.
3 files changed