commit fa7752986da7a5cdd4f0cd9aff6c315ae0c83c0e
author Christopher Ferris <cferris@google.com> Fri Oct 23 15:42:27 2015 -0700
committer Christopher Ferris <cferris@google.com> Fri Oct 23 16:41:17 2015 -0700
tree 069fef01477831a4f74098dda5fef9130bc92ceb
parent ca430d9787f1c11c2df8e908c64fe2ef2e6d54ed

Fix arm64 fenv warnings, and make warnings errors.

Even though the control registers being read/written in fenv.c only
have 32 bits that are used, the instructions take a 64 bit register.
Make sure the inline assembler in the macros use 64 bit values.

Verified that before the change and after the change, the disassembly
is exactly the same.

In addition, add -Werror to the cflags.

Change-Id: I6603779327488c23e3aab13300edf2e02b101916

libm/Android.mk

diff --git a/libm/Android.mk b/libm/Android.mk
index fb8df07..f6c49aa 100644
--- a/libm/Android.mk
+++ b/libm/Android.mk
@@ -485,6 +485,7 @@
     -D__BIONIC_NO_MATH_INLINES \
     -DFLT_EVAL_METHOD=0 \
     -include $(LOCAL_PATH)/freebsd-compat.h \
+    -Werror \
     -Wno-missing-braces \
     -Wno-parentheses \
     -Wno-sign-compare \

libm/arm64/fenv.c

diff --git a/libm/arm64/fenv.c b/libm/arm64/fenv.c
index ce560a7..19a2393 100644
--- a/libm/arm64/fenv.c
+++ b/libm/arm64/fenv.c
@@ -26,6 +26,7 @@
  * $FreeBSD: libm/aarch64/fenv.c $
  */
 
+#include <stdint.h>
 #include <fenv.h>
 
 #define FPCR_EXCEPT_SHIFT 8
@@ -38,10 +39,20 @@
 typedef __uint32_t fpu_control_t;   // FPCR, Floating-point Control Register.
 typedef __uint32_t fpu_status_t;    // FPSR, Floating-point Status Register.
 
-#define __get_fpcr(__fpcr) __asm__ __volatile__("mrs %0,fpcr" : "=r" (__fpcr))
-#define __get_fpsr(__fpsr) __asm__ __volatile__("mrs %0,fpsr" : "=r" (__fpsr))
-#define __set_fpcr(__fpcr) __asm__ __volatile__("msr fpcr,%0" : :"ri" (__fpcr))
-#define __set_fpsr(__fpsr) __asm__ __volatile__("msr fpsr,%0" : :"ri" (__fpsr))
+#define __get(REGISTER, __value) { \
+  uint64_t __value64; \
+  __asm__ __volatile__("mrs %0," REGISTER : "=r" (__value64)); \
+  __value = (__uint32_t) __value64; \
+}
+#define __get_fpcr(__fpcr) __get("fpcr", __fpcr)
+#define __get_fpsr(__fpsr) __get("fpsr", __fpsr)
+
+#define __set(REGISTER, __value) { \
+  uint64_t __value64 = __value; \
+  __asm__ __volatile__("msr " REGISTER ",%0" : : "ri" (__value64)); \
+}
+#define __set_fpcr(__fpcr) __set("fpcr", __fpcr)
+#define __set_fpsr(__fpsr) __set("fpsr", __fpsr)
 
 int fegetenv(fenv_t* envp) {
   __get_fpcr(envp->__control);