| Raghu Gandham | 82fa43f | 2012-03-27 11:37:17 -0700 | [diff] [blame^] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __NEC_VR41XX_IRQ_H |
| 20 | #define __NEC_VR41XX_IRQ_H |
| 21 | #define MIPS_CPU_IRQ_BASE 0 |
| 22 | #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) |
| 23 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 24 | #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) |
| 25 | #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) |
| 26 | #define INT0_IRQ MIPS_CPU_IRQ(2) |
| 27 | #define INT1_IRQ MIPS_CPU_IRQ(3) |
| 28 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 29 | #define INT2_IRQ MIPS_CPU_IRQ(4) |
| 30 | #define INT3_IRQ MIPS_CPU_IRQ(5) |
| 31 | #define INT4_IRQ MIPS_CPU_IRQ(6) |
| 32 | #define TIMER_IRQ MIPS_CPU_IRQ(7) |
| 33 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 34 | #define SYSINT1_IRQ_BASE 8 |
| 35 | #define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x)) |
| 36 | #define BATTRY_IRQ SYSINT1_IRQ(0) |
| 37 | #define POWER_IRQ SYSINT1_IRQ(1) |
| 38 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 39 | #define RTCLONG1_IRQ SYSINT1_IRQ(2) |
| 40 | #define ELAPSEDTIME_IRQ SYSINT1_IRQ(3) |
| 41 | #define PIU_IRQ SYSINT1_IRQ(5) |
| 42 | #define AIU_IRQ SYSINT1_IRQ(6) |
| 43 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 44 | #define KIU_IRQ SYSINT1_IRQ(7) |
| 45 | #define GIUINT_IRQ SYSINT1_IRQ(8) |
| 46 | #define SIU_IRQ SYSINT1_IRQ(9) |
| 47 | #define BUSERR_IRQ SYSINT1_IRQ(10) |
| 48 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 49 | #define SOFTINT_IRQ SYSINT1_IRQ(11) |
| 50 | #define CLKRUN_IRQ SYSINT1_IRQ(12) |
| 51 | #define DOZEPIU_IRQ SYSINT1_IRQ(13) |
| 52 | #define SYSINT1_IRQ_LAST DOZEPIU_IRQ |
| 53 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 54 | #define SYSINT2_IRQ_BASE 24 |
| 55 | #define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x)) |
| 56 | #define RTCLONG2_IRQ SYSINT2_IRQ(0) |
| 57 | #define LED_IRQ SYSINT2_IRQ(1) |
| 58 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 59 | #define HSP_IRQ SYSINT2_IRQ(2) |
| 60 | #define TCLOCK_IRQ SYSINT2_IRQ(3) |
| 61 | #define FIR_IRQ SYSINT2_IRQ(4) |
| 62 | #define CEU_IRQ SYSINT2_IRQ(4) |
| 63 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 64 | #define DSIU_IRQ SYSINT2_IRQ(5) |
| 65 | #define PCI_IRQ SYSINT2_IRQ(6) |
| 66 | #define SCU_IRQ SYSINT2_IRQ(7) |
| 67 | #define CSI_IRQ SYSINT2_IRQ(8) |
| 68 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 69 | #define BCU_IRQ SYSINT2_IRQ(9) |
| 70 | #define ETHERNET_IRQ SYSINT2_IRQ(10) |
| 71 | #define SYSINT2_IRQ_LAST ETHERNET_IRQ |
| 72 | #define GIU_IRQ_BASE 40 |
| 73 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 74 | #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) |
| 75 | #define GIU_IRQ_LAST GIU_IRQ(31) |
| 76 | #define VRC4173_IRQ_BASE 72 |
| 77 | #define VRC4173_IRQ(x) (VRC4173_IRQ_BASE + (x)) |
| 78 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 79 | #define VRC4173_USB_IRQ VRC4173_IRQ(0) |
| 80 | #define VRC4173_PCMCIA2_IRQ VRC4173_IRQ(1) |
| 81 | #define VRC4173_PCMCIA1_IRQ VRC4173_IRQ(2) |
| 82 | #define VRC4173_PS2CH2_IRQ VRC4173_IRQ(3) |
| 83 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 84 | #define VRC4173_PS2CH1_IRQ VRC4173_IRQ(4) |
| 85 | #define VRC4173_PIU_IRQ VRC4173_IRQ(5) |
| 86 | #define VRC4173_AIU_IRQ VRC4173_IRQ(6) |
| 87 | #define VRC4173_KIU_IRQ VRC4173_IRQ(7) |
| 88 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 89 | #define VRC4173_GIU_IRQ VRC4173_IRQ(8) |
| 90 | #define VRC4173_AC97_IRQ VRC4173_IRQ(9) |
| 91 | #define VRC4173_AC97INT1_IRQ VRC4173_IRQ(10) |
| 92 | #define VRC4173_DOZEPIU_IRQ VRC4173_IRQ(13) |
| 93 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 94 | #define VRC4173_IRQ_LAST VRC4173_DOZEPIU_IRQ |
| 95 | #endif |