| Raghu Gandham | 82fa43f | 2012-03-27 11:37:17 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H |
| 20 | #define __ASM_MIPS_BOARDS_MSC01_PCI_H |
| 21 | #define MSC01_PCI_ID_OFS 0x0000 |
| 22 | #define MSC01_PCI_SC2PMBASL_OFS 0x0208 |
| 23 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 24 | #define MSC01_PCI_SC2PMMSKL_OFS 0x0218 |
| 25 | #define MSC01_PCI_SC2PMMAPL_OFS 0x0228 |
| 26 | #define MSC01_PCI_SC2PIOBASL_OFS 0x0248 |
| 27 | #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258 |
| 28 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 29 | #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268 |
| 30 | #define MSC01_PCI_P2SCMSKL_OFS 0x0308 |
| 31 | #define MSC01_PCI_P2SCMAPL_OFS 0x0318 |
| 32 | #define MSC01_PCI_INTCFG_OFS 0x0600 |
| 33 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 34 | #define MSC01_PCI_INTSTAT_OFS 0x0608 |
| 35 | #define MSC01_PCI_CFGADDR_OFS 0x0610 |
| 36 | #define MSC01_PCI_CFGDATA_OFS 0x0618 |
| 37 | #define MSC01_PCI_IACK_OFS 0x0620 |
| 38 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 39 | #define MSC01_PCI_HEAD0_OFS 0x2000 |
| 40 | #define MSC01_PCI_HEAD1_OFS 0x2008 |
| 41 | #define MSC01_PCI_HEAD2_OFS 0x2010 |
| 42 | #define MSC01_PCI_HEAD3_OFS 0x2018 |
| 43 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 44 | #define MSC01_PCI_HEAD4_OFS 0x2020 |
| 45 | #define MSC01_PCI_HEAD5_OFS 0x2028 |
| 46 | #define MSC01_PCI_HEAD6_OFS 0x2030 |
| 47 | #define MSC01_PCI_HEAD7_OFS 0x2038 |
| 48 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 49 | #define MSC01_PCI_HEAD8_OFS 0x2040 |
| 50 | #define MSC01_PCI_HEAD9_OFS 0x2048 |
| 51 | #define MSC01_PCI_HEAD10_OFS 0x2050 |
| 52 | #define MSC01_PCI_HEAD11_OFS 0x2058 |
| 53 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 54 | #define MSC01_PCI_HEAD12_OFS 0x2060 |
| 55 | #define MSC01_PCI_HEAD13_OFS 0x2068 |
| 56 | #define MSC01_PCI_HEAD14_OFS 0x2070 |
| 57 | #define MSC01_PCI_HEAD15_OFS 0x2078 |
| 58 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 59 | #define MSC01_PCI_BAR0_OFS 0x2220 |
| 60 | #define MSC01_PCI_CFG_OFS 0x2380 |
| 61 | #define MSC01_PCI_SWAP_OFS 0x2388 |
| 62 | #define MSC01_PCI_ID_ID_SHF 16 |
| 63 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 64 | #define MSC01_PCI_ID_ID_MSK 0x00ff0000 |
| 65 | #define MSC01_PCI_ID_ID_HOSTBRIDGE 82 |
| 66 | #define MSC01_PCI_ID_MAR_SHF 8 |
| 67 | #define MSC01_PCI_ID_MAR_MSK 0x0000ff00 |
| 68 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 69 | #define MSC01_PCI_ID_MIR_SHF 0 |
| 70 | #define MSC01_PCI_ID_MIR_MSK 0x000000ff |
| 71 | #define MSC01_PCI_SC2PMBASL_BAS_SHF 24 |
| 72 | #define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000 |
| 73 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 74 | #define MSC01_PCI_SC2PMMSKL_MSK_SHF 24 |
| 75 | #define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000 |
| 76 | #define MSC01_PCI_SC2PMMAPL_MAP_SHF 24 |
| 77 | #define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000 |
| 78 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 79 | #define MSC01_PCI_SC2PIOBASL_BAS_SHF 24 |
| 80 | #define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000 |
| 81 | #define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24 |
| 82 | #define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000 |
| 83 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 84 | #define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24 |
| 85 | #define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000 |
| 86 | #define MSC01_PCI_P2SCMSKL_MSK_SHF 24 |
| 87 | #define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000 |
| 88 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 89 | #define MSC01_PCI_P2SCMAPL_MAP_SHF 24 |
| 90 | #define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000 |
| 91 | #define MSC01_PCI_INTCFG_RST_SHF 10 |
| 92 | #define MSC01_PCI_INTCFG_RST_MSK 0x00000400 |
| 93 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 94 | #define MSC01_PCI_INTCFG_RST_BIT 0x00000400 |
| 95 | #define MSC01_PCI_INTCFG_MWE_SHF 9 |
| 96 | #define MSC01_PCI_INTCFG_MWE_MSK 0x00000200 |
| 97 | #define MSC01_PCI_INTCFG_MWE_BIT 0x00000200 |
| 98 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 99 | #define MSC01_PCI_INTCFG_DTO_SHF 8 |
| 100 | #define MSC01_PCI_INTCFG_DTO_MSK 0x00000100 |
| 101 | #define MSC01_PCI_INTCFG_DTO_BIT 0x00000100 |
| 102 | #define MSC01_PCI_INTCFG_MA_SHF 7 |
| 103 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 104 | #define MSC01_PCI_INTCFG_MA_MSK 0x00000080 |
| 105 | #define MSC01_PCI_INTCFG_MA_BIT 0x00000080 |
| 106 | #define MSC01_PCI_INTCFG_TA_SHF 6 |
| 107 | #define MSC01_PCI_INTCFG_TA_MSK 0x00000040 |
| 108 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 109 | #define MSC01_PCI_INTCFG_TA_BIT 0x00000040 |
| 110 | #define MSC01_PCI_INTCFG_RTY_SHF 5 |
| 111 | #define MSC01_PCI_INTCFG_RTY_MSK 0x00000020 |
| 112 | #define MSC01_PCI_INTCFG_RTY_BIT 0x00000020 |
| 113 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 114 | #define MSC01_PCI_INTCFG_MWP_SHF 4 |
| 115 | #define MSC01_PCI_INTCFG_MWP_MSK 0x00000010 |
| 116 | #define MSC01_PCI_INTCFG_MWP_BIT 0x00000010 |
| 117 | #define MSC01_PCI_INTCFG_MRP_SHF 3 |
| 118 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 119 | #define MSC01_PCI_INTCFG_MRP_MSK 0x00000008 |
| 120 | #define MSC01_PCI_INTCFG_MRP_BIT 0x00000008 |
| 121 | #define MSC01_PCI_INTCFG_SWP_SHF 2 |
| 122 | #define MSC01_PCI_INTCFG_SWP_MSK 0x00000004 |
| 123 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 124 | #define MSC01_PCI_INTCFG_SWP_BIT 0x00000004 |
| 125 | #define MSC01_PCI_INTCFG_SRP_SHF 1 |
| 126 | #define MSC01_PCI_INTCFG_SRP_MSK 0x00000002 |
| 127 | #define MSC01_PCI_INTCFG_SRP_BIT 0x00000002 |
| 128 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 129 | #define MSC01_PCI_INTCFG_SE_SHF 0 |
| 130 | #define MSC01_PCI_INTCFG_SE_MSK 0x00000001 |
| 131 | #define MSC01_PCI_INTCFG_SE_BIT 0x00000001 |
| 132 | #define MSC01_PCI_INTSTAT_RST_SHF 10 |
| 133 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 134 | #define MSC01_PCI_INTSTAT_RST_MSK 0x00000400 |
| 135 | #define MSC01_PCI_INTSTAT_RST_BIT 0x00000400 |
| 136 | #define MSC01_PCI_INTSTAT_MWE_SHF 9 |
| 137 | #define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200 |
| 138 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 139 | #define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200 |
| 140 | #define MSC01_PCI_INTSTAT_DTO_SHF 8 |
| 141 | #define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100 |
| 142 | #define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100 |
| 143 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 144 | #define MSC01_PCI_INTSTAT_MA_SHF 7 |
| 145 | #define MSC01_PCI_INTSTAT_MA_MSK 0x00000080 |
| 146 | #define MSC01_PCI_INTSTAT_MA_BIT 0x00000080 |
| 147 | #define MSC01_PCI_INTSTAT_TA_SHF 6 |
| 148 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 149 | #define MSC01_PCI_INTSTAT_TA_MSK 0x00000040 |
| 150 | #define MSC01_PCI_INTSTAT_TA_BIT 0x00000040 |
| 151 | #define MSC01_PCI_INTSTAT_RTY_SHF 5 |
| 152 | #define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020 |
| 153 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 154 | #define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020 |
| 155 | #define MSC01_PCI_INTSTAT_MWP_SHF 4 |
| 156 | #define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010 |
| 157 | #define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010 |
| 158 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 159 | #define MSC01_PCI_INTSTAT_MRP_SHF 3 |
| 160 | #define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008 |
| 161 | #define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008 |
| 162 | #define MSC01_PCI_INTSTAT_SWP_SHF 2 |
| 163 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 164 | #define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004 |
| 165 | #define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004 |
| 166 | #define MSC01_PCI_INTSTAT_SRP_SHF 1 |
| 167 | #define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002 |
| 168 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 169 | #define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002 |
| 170 | #define MSC01_PCI_INTSTAT_SE_SHF 0 |
| 171 | #define MSC01_PCI_INTSTAT_SE_MSK 0x00000001 |
| 172 | #define MSC01_PCI_INTSTAT_SE_BIT 0x00000001 |
| 173 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 174 | #define MSC01_PCI_CFGADDR_BNUM_SHF 16 |
| 175 | #define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000 |
| 176 | #define MSC01_PCI_CFGADDR_DNUM_SHF 11 |
| 177 | #define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800 |
| 178 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 179 | #define MSC01_PCI_CFGADDR_FNUM_SHF 8 |
| 180 | #define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700 |
| 181 | #define MSC01_PCI_CFGADDR_RNUM_SHF 2 |
| 182 | #define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc |
| 183 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 184 | #define MSC01_PCI_CFGDATA_DATA_SHF 0 |
| 185 | #define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff |
| 186 | #define MSC01_PCI_BAR0_SIZE_SHF 4 |
| 187 | #define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0 |
| 188 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 189 | #define MSC01_PCI_BAR0_P_SHF 3 |
| 190 | #define MSC01_PCI_BAR0_P_MSK 0x00000008 |
| 191 | #define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK |
| 192 | #define MSC01_PCI_BAR0_D_SHF 1 |
| 193 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 194 | #define MSC01_PCI_BAR0_D_MSK 0x00000006 |
| 195 | #define MSC01_PCI_BAR0_T_SHF 0 |
| 196 | #define MSC01_PCI_BAR0_T_MSK 0x00000001 |
| 197 | #define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK |
| 198 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 199 | #define MSC01_PCI_CFG_RA_SHF 17 |
| 200 | #define MSC01_PCI_CFG_RA_MSK 0x00020000 |
| 201 | #define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK |
| 202 | #define MSC01_PCI_CFG_G_SHF 16 |
| 203 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 204 | #define MSC01_PCI_CFG_G_MSK 0x00010000 |
| 205 | #define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK |
| 206 | #define MSC01_PCI_CFG_EN_SHF 15 |
| 207 | #define MSC01_PCI_CFG_EN_MSK 0x00008000 |
| 208 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 209 | #define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK |
| 210 | #define MSC01_PCI_CFG_MAXRTRY_SHF 0 |
| 211 | #define MSC01_PCI_CFG_MAXRTRY_MSK 0x00000fff |
| 212 | #define MSC01_PCI_SWAP_IO_SHF 18 |
| 213 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 214 | #define MSC01_PCI_SWAP_IO_MSK 0x000c0000 |
| 215 | #define MSC01_PCI_SWAP_MEM_SHF 16 |
| 216 | #define MSC01_PCI_SWAP_MEM_MSK 0x00030000 |
| 217 | #define MSC01_PCI_SWAP_BAR0_SHF 0 |
| 218 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 219 | #define MSC01_PCI_SWAP_BAR0_MSK 0x00000003 |
| 220 | #define MSC01_PCI_SWAP_NOSWAP 0 |
| 221 | #define MSC01_PCI_SWAP_BYTESWAP 1 |
| 222 | #define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 |
| 223 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 224 | #define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000 |
| 225 | #define MSC01_PCI_REG_BASE _pcictrl_msc |
| 226 | #define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) |
| 227 | #define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) |
| 228 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 229 | #define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) |
| 230 | #define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) |
| 231 | #define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS) |
| 232 | #define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS) |
| 233 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 234 | #define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS) |
| 235 | #define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS) |
| 236 | #define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS) |
| 237 | #define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS) |
| 238 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 239 | #define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS) |
| 240 | #define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS) |
| 241 | #define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS) |
| 242 | #define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS) |
| 243 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 244 | #define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS) |
| 245 | #define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS) |
| 246 | #define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS) |
| 247 | #define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS) |
| 248 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 249 | #define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS) |
| 250 | #define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS) |
| 251 | #define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS) |
| 252 | #define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS) |
| 253 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 254 | #define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS) |
| 255 | #define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS) |
| 256 | #define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS) |
| 257 | #define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS) |
| 258 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 259 | #define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS) |
| 260 | #define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) |
| 261 | #define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) |
| 262 | #define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) |
| 263 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 264 | #define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) |
| 265 | #define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS) |
| 266 | #define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS) |
| 267 | #define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) |
| 268 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 269 | #define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) |
| 270 | #endif |