| Christopher Ferris | 9ce2884 | 2018-10-25 12:11:39 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef _UAPI_LINUX_FPGA_DFL_H |
| 20 | #define _UAPI_LINUX_FPGA_DFL_H |
| 21 | #include <linux/types.h> |
| 22 | #include <linux/ioctl.h> |
| 23 | #define DFL_FPGA_API_VERSION 0 |
| 24 | #define DFL_FPGA_MAGIC 0xB6 |
| 25 | #define DFL_FPGA_BASE 0 |
| 26 | #define DFL_PORT_BASE 0x40 |
| 27 | #define DFL_FME_BASE 0x80 |
| 28 | #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) |
| 29 | #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) |
| 30 | #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) |
| 31 | struct dfl_fpga_port_info { |
| 32 | __u32 argsz; |
| 33 | __u32 flags; |
| 34 | __u32 num_regions; |
| 35 | __u32 num_umsgs; |
| 36 | }; |
| 37 | #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1) |
| 38 | struct dfl_fpga_port_region_info { |
| 39 | __u32 argsz; |
| 40 | __u32 flags; |
| 41 | #define DFL_PORT_REGION_READ (1 << 0) |
| 42 | #define DFL_PORT_REGION_WRITE (1 << 1) |
| 43 | #define DFL_PORT_REGION_MMAP (1 << 2) |
| 44 | __u32 index; |
| 45 | #define DFL_PORT_REGION_INDEX_AFU 0 |
| 46 | #define DFL_PORT_REGION_INDEX_STP 1 |
| 47 | __u32 padding; |
| 48 | __u64 size; |
| 49 | __u64 offset; |
| 50 | }; |
| 51 | #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2) |
| 52 | struct dfl_fpga_port_dma_map { |
| 53 | __u32 argsz; |
| 54 | __u32 flags; |
| 55 | __u64 user_addr; |
| 56 | __u64 length; |
| 57 | __u64 iova; |
| 58 | }; |
| 59 | #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3) |
| 60 | struct dfl_fpga_port_dma_unmap { |
| 61 | __u32 argsz; |
| 62 | __u32 flags; |
| 63 | __u64 iova; |
| 64 | }; |
| 65 | #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4) |
| 66 | struct dfl_fpga_fme_port_pr { |
| 67 | __u32 argsz; |
| 68 | __u32 flags; |
| 69 | __u32 port_id; |
| 70 | __u32 buffer_size; |
| 71 | __u64 buffer_address; |
| 72 | }; |
| 73 | #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0) |
| 74 | #endif |