)]}'
{
  "log": [
    {
      "commit": "d1973ca51325393f304e82a4d79874f33e54ac16",
      "tree": "75a657d895a41aa4855a06ef1e0e986c963e0eef",
      "parents": [
        "5b4884fac90753c68d401de73036c2de919958eb"
      ],
      "author": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Tue Jan 21 19:50:58 2014 -0800"
      },
      "committer": {
        "name": "Colin Cross",
        "email": "ccross@android.com",
        "time": "Thu Jan 23 18:35:39 2014 -0800"
      },
      "message": "bionic: rename aarch64 target to arm64\n\nRename aarch64 build targets to arm64.  The gcc toolchain is still\naarch64.\n\nChange-Id: Ia92d8a50824e5329cf00fd6f4f92eae112b7f3a3\n"
    },
    {
      "commit": "b5e211031b69963a5f72ff369c66dc325a03e740",
      "tree": "4459ac3233abccfcdce9f2dc2591aeabadc16ede",
      "parents": [
        "ebc1c76d77dd604f16126e66b2171e8ee6fa1d22",
        "bf3ec9ad52a5ccaccdae843a94f964f3a7624ecd"
      ],
      "author": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Tue Jan 14 01:01:40 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Jan 14 01:01:41 2014 +0000"
      },
      "message": "Merge \"AArch64: Use LDXR/STXR instead of LDAXR/STLXR for bionic_atomic_cmpxchg()\""
    },
    {
      "commit": "845c778fa6ebb3ff3feaac0c268d93f4017c0cda",
      "tree": "1c38223ae764a3cb90650a916af849f64b8a00be",
      "parents": [
        "1afb375d30cadf5dfcb5dfe352527e2a1147c79f"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Dec 19 11:57:10 2013 +0000"
      },
      "committer": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Thu Dec 19 11:39:01 2013 -0800"
      },
      "message": "ARM: Change dmb domain for bionic_atomic_barrier()\n\nThis patch changes the domain that the memory barrier operates on. Assumes\nthat the scope of bionic_atomic_barrier() does not include device memory,\nmemory shared with the GPU or any other memory external to the processor\ncluster.\n\nChange-Id: I291e741c98a64c86f3a3cf99811bbf1e714ac9aa\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "bf3ec9ad52a5ccaccdae843a94f964f3a7624ecd",
      "tree": "61952ac46346f7149c5b2694b5341978262bbe74",
      "parents": [
        "81ddd14381b09f171c006ebcbba15b3c1baf2a9f"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Thu Dec 19 11:46:17 2013 +0000"
      },
      "committer": {
        "name": "David Butcher",
        "email": "david.butcher@arm.com",
        "time": "Thu Dec 19 18:32:53 2013 +0000"
      },
      "message": "AArch64: Use LDXR/STXR instead of LDAXR/STLXR for bionic_atomic_cmpxchg()\n\nThe bionic_atomic_cmpxchg() API states that the cmpxchg() will be done without\nexplicit memory barriers. LDAXR/STLXR semantics involve half barriers for\nload/store.\n\nThis patch optimises cmpxchg() by using LDXR/STXR and avoiding unnecessary half\nbariers. It also fixes the clobber list for all the bionic_atomic_*() functions.\n\nChange-Id: Iae9468965785cfeeec791d52f1e8cbc524adb682\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    },
    {
      "commit": "1924a5c92e1791bdb6a5e9c09541a5a9a343983b",
      "tree": "0e069b3e78f42df4eda54abd28bdc2df5e6a8ced",
      "parents": [
        "3937d41561206430373c4b3e0690d6f81b536412"
      ],
      "author": {
        "name": "Serban Constantinescu",
        "email": "serban.constantinescu@arm.com",
        "time": "Tue Oct 08 19:29:55 2013 +0100"
      },
      "committer": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Mon Dec 16 13:09:33 2013 -0800"
      },
      "message": "AArch64: Add support for AArch64 atomic operations\n\nThis patch adds support for AArch64 atomic operations. Some\nof the stubs use the lightweight store/load exclusive.\n\nChange-Id: Iaf704d048b2dc15bf08cf8e4f0c3ea9f2052fe13\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n"
    }
  ]
}