)]}'
{
  "commit": "aba11fc50c925bbd6fb25d54eae2f86277a3b107",
  "tree": "52c85a46371ca4ef05042600507ecd5bdcfa2842",
  "parents": [
    "fc4033b2f8b1482022bff3d05505a1b1631bb6de"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Jun 19 09:40:31 2008 -0500"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Jun 26 01:49:03 2008 -0500"
  },
  "message": "powerpc/e500mc: flush L2 on NAP for e500mc\n\nIf we have an L2CSR register (e500mc) we need to flush the L2 before going\nto nap.  We use the HW flush mechanism provided in that register.\n\nThe code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by\nany code in the kernel.  Additionally we didn\u0027t reuse the exist L2CR\nfeature bit as this is intended for the 7xxx L2CR register and L2CSR\nis part of the new Freescale \"Book-E\" registers.\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "267adec2491b38f917a93b502ae8f12650447e1b",
      "old_mode": 33188,
      "old_path": "arch/powerpc/kernel/idle_e500.S",
      "new_id": "06304034b3939e63cb619849fc5d80ebd6b07ce4",
      "new_mode": 33188,
      "new_path": "arch/powerpc/kernel/idle_e500.S"
    },
    {
      "type": "modify",
      "old_id": "18feb63dd3c07e33b3bdc5e83974c1f859e9ce92",
      "old_mode": 33188,
      "old_path": "include/asm-powerpc/cputable.h",
      "new_id": "9106113ae0b5bc5dd237329442721e1103ba909c",
      "new_mode": 33188,
      "new_path": "include/asm-powerpc/cputable.h"
    },
    {
      "type": "modify",
      "old_id": "a5e8903bbc874d62a4caffd537f04d1d6302b043",
      "old_mode": 33188,
      "old_path": "include/asm-powerpc/reg_booke.h",
      "new_id": "be980f4ee4956cd20d00fe107c103d7b2a58d21a",
      "new_mode": 33188,
      "new_path": "include/asm-powerpc/reg_booke.h"
    }
  ]
}