)]}'
{
  "commit": "b6018958a57f6621d6979c4384e42a3df636beed",
  "tree": "84806c5f1b5839e66edcfc811927b137fda7a247",
  "parents": [
    "e10a854c4602072c34c03380b99da0a3ee15682c"
  ],
  "author": {
    "name": "Cliff Brake",
    "email": "cbrake@bec-systems.com",
    "time": "Thu Jan 22 17:07:03 2009 -0500"
  },
  "committer": {
    "name": "Pierre Ossman",
    "email": "drzeus@drzeus.cx",
    "time": "Mon Feb 02 20:57:07 2009 +0100"
  },
  "message": "pxamci: enable DMA for write ops after CMD/RESP\n\nWith the PXA270 MMC hardware, there seems to be an issue of\ndata corruption on writes where a 4KB data block is offset\nby one byte.\n\nIf we delay enabling the DMA for writes until after the CMD/RESP\nhas finished, the problem seems to be fixed.\n\nrelated to PXA270 Erratum #91\n\nTested-by: Vernon Sauder \u003cVernonInHand@gmail.com\u003e\nSigned-off-by: Cliff Brake \u003ccbrake@bec-systems.com\u003e\nAcked-by: Eric Miao \u003ceric.miao@marvell.com\u003e\nSigned-off-by: Pierre Ossman \u003cdrzeus@drzeus.cx\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3000422f4d8119ec363fd1eafefa34bd9f6573d1",
      "old_mode": 33188,
      "old_path": "drivers/mmc/host/pxamci.c",
      "new_id": "9702ad3774cf90ae1065d2d8d2a8e271c240aaae",
      "new_mode": 33188,
      "new_path": "drivers/mmc/host/pxamci.c"
    }
  ]
}