)]}'
{
  "commit": "d30cecbcbe149a36a354757cea835c1bb28689cf",
  "tree": "695c69480dfa8e083cf567aad02bef2a5a35cfca",
  "parents": [
    "22242681cff52bfb7cba5d2a37b91802be7a4e4c"
  ],
  "author": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Wed May 27 17:29:37 2009 +0100"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Mon Nov 02 12:00:01 2009 +0100"
  },
  "message": "MIPS: Don\u0027t write ones to reserved entryhi bits.\n\nWe\u0027ve silently been relying on the hardware chopping off excess, reserved\nASID bits for no better reason that it saving an instruction.  Because we\nalready have:\n\n#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) \u0026 ASID_MASK)\n\nin \u003casm/mmu_context.h\u003e.\n\nWe can use a cleanup to avoid writing non-zero bits into the reserved\nentryhi bits.  This avoid triggering some debugging assertion in the\nCavium simulator.\n\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d9743536a6217c09e413fec50ff00647e842fadc",
      "old_mode": 33188,
      "old_path": "arch/mips/include/asm/mmu_context.h",
      "new_id": "ed331c2e48826c6a87cb0c9c1823d419b85264c8",
      "new_mode": 33188,
      "new_path": "arch/mips/include/asm/mmu_context.h"
    }
  ]
}