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review.evervolv.com / android_kernel_grouper / 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 / . / arch / mips / jmr3927 / rbhma3100 / kgdb_io.c
blob: 269a42deae062e23caf8b8c36b09d89c39e02ba7 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame^]1/*
2 * BRIEF MODULE DESCRIPTION
3 * Low level uart routines to directly access a TX[34]927 SIO.
4 *
5 * Copyright 2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ahennessy@mvista.com or source@mvista.com
8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
10 *
11 * Copyright (C) 2000-2001 Toshiba Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33
34#include <linux/types.h>
35#include <asm/jmr3927/txx927.h>
36#include <asm/jmr3927/tx3927.h>
37#include <asm/jmr3927/jmr3927.h>
38
39#define TIMEOUT 0xffffff
40#define SLOW_DOWN
41
42static const char digits[16] = "0123456789abcdef";
43
44#ifdef SLOW_DOWN
45#define slow_down() { int k; for (k=0; k<10000; k++); }
46#else
47#define slow_down()
48#endif
49
50static int remoteDebugInitialized = 0;
51
52int putDebugChar(unsigned char c)
53{
54 int i = 0;
55
56 if (!remoteDebugInitialized) {
57 remoteDebugInitialized = 1;
58 debugInit(38400);
59 }
60
61 do {
62 slow_down();
63 i++;
64 if (i>TIMEOUT) {
65 break;
66 }
67 } while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
68 tx3927_sioptr(0)->tfifo = c;
69
70 return 1;
71}
72
73unsigned char getDebugChar(void)
74{
75 int i = 0;
76 int dicr;
77 char c;
78
79 if (!remoteDebugInitialized) {
80 remoteDebugInitialized = 1;
81 debugInit(38400);
82 }
83
84 /* diable RX int. */
85 dicr = tx3927_sioptr(0)->dicr;
86 tx3927_sioptr(0)->dicr = 0;
87
88 do {
89 slow_down();
90 i++;
91 if (i>TIMEOUT) {
92 break;
93 }
94 } while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
95 ;
96 c = tx3927_sioptr(0)->rfifo;
97
98 /* clear RX int. status */
99 tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
100 /* enable RX int. */
101 tx3927_sioptr(0)->dicr = dicr;
102
103 return c;
104}
105
106void debugInit(int baud)
107{
108 /*
109 volatile unsigned long lcr;
110 volatile unsigned long dicr;
111 volatile unsigned long disr;
112 volatile unsigned long cisr;
113 volatile unsigned long fcr;
114 volatile unsigned long flcr;
115 volatile unsigned long bgr;
116 volatile unsigned long tfifo;
117 volatile unsigned long rfifo;
118 */
119
120 tx3927_sioptr(0)->lcr = 0x020;
121 tx3927_sioptr(0)->dicr = 0;
122 tx3927_sioptr(0)->disr = 0x4100;
123 tx3927_sioptr(0)->cisr = 0x014;
124 tx3927_sioptr(0)->fcr = 0;
125 tx3927_sioptr(0)->flcr = 0x02;
126 tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
127 TXx927_SIBGR_BCLK_T0;
128#if 0
129 /*
130 * Reset the UART.
131 */
132 tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
133 while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
134 ;
135
136 /*
137 * and set the speed of the serial port
138 * (currently hardwired to 9600 8N1
139 */
140
141 tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
142 TXx927_SILCR_USBL_1BIT |
143 TXx927_SILCR_SCS_IMCLK_BG;
144 tx3927_sioptr(0)->bgr =
145 ((JMR3927_BASE_BAUD + baud / 2) / baud) |
146 TXx927_SIBGR_BCLK_T0;
147
148 /* HW RTS/CTS control */
149 if (ser->flags & ASYNC_HAVE_CTS_LINE)
150 tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
151 TXx927_SIFLCR_RTSTL_MAX /* 15 */;
152 /* Enable RX/TX */
153 tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
154#endif
155}