)]}'
{
  "commit": "a53f89545d62a27443f2d836be81ec6db68d12fd",
  "tree": "5ef778455d17da0c050f205b61341b23d2eafd72",
  "parents": [
    "116bf34754f1ef505888f8250aa6a4b18e0106bc"
  ],
  "author": {
    "name": "Jian Hu",
    "email": "jian.hu@amlogic.com",
    "time": "Thu Jun 14 17:44:24 2018 +0800"
  },
  "committer": {
    "name": "Yixun Lan",
    "email": "yixun.lan@amlogic.com",
    "time": "Wed Jul 18 02:32:38 2018 -0700"
  },
  "message": "clk: txl: initial add clock driver\n\nPD#168480: clk: txl: initial add clock driver\n\nremove CLK_SET_RATE_PARENT flag for spicc.\nIf add CLK_SET_RATE_PARENT, it will change clk81 rate when set\nspicc clock rate.\n\nChange-Id: I80fec2c6d10611994ff40b06307e39b51ddb5a1a\nSigned-off-by: Jian Hu \u003cjian.hu@amlogic.com\u003e\nSigned-off-by: Bo Yang \u003cbo.yang@amlogic.com\u003e\n",
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