| commit | fcb2ff98055e821c34ceacec671cc2d89d4fa3dd | [log] [tgz] |
|---|---|---|
| author | Shunzhou Jiang <shunzhou.jiang@amlogic.com> | Fri Nov 16 15:54:52 2018 +0800 |
| committer | Dongjin Kim <tobetter@gmail.com> | Fri Dec 21 13:05:18 2018 +0900 |
| tree | cac2928cce7011de72bf21736f9dcd5afd1bcac0 | |
| parent | 6bd599c6163ec11ef61f49394b9c27eb54518384 [diff] |
clk: g12a/g12b: fix 32bit set mpll clk overflow [1/1] PD#SWPL-1933 Problem: 32bit system clk overflow Solution: let mpll clock not overflow Verify: g12b Change-Id: Ie1c7c611e637776348bb35a3e0c1624cee57716f Signed-off-by: shunzhou.jiang <shunzhou.jiang@amlogic.com>