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review.evervolv.com / android_kernel_htc_m7 / 1e3d31172fce4905d8aff867d5b714a6ad3cf2ee / . / include / linux / qcedev.h
blob: 3d0371a249dfd1de0ca5574407c968ef3860db0f [file] [log] [blame]
Nicholas Flintham1e3d3112013-04-10 10:48:38 +0100[diff] [blame^]1#ifndef __QCEDEV__H
2#define __QCEDEV__H
3
4#include <linux/types.h>
5#include <linux/ioctl.h>
6
7#define QCEDEV_MAX_SHA_BLOCK_SIZE 64
8#define QCEDEV_MAX_BEARER 31
9#define QCEDEV_MAX_KEY_SIZE 64
10#define QCEDEV_MAX_IV_SIZE 32
11
12#define QCEDEV_MAX_BUFFERS 16
13#define QCEDEV_MAX_SHA_DIGEST 32
14
15#define QCEDEV_USE_PMEM 1
16#define QCEDEV_NO_PMEM 0
17
18#define QCEDEV_AES_KEY_128 16
19#define QCEDEV_AES_KEY_192 24
20#define QCEDEV_AES_KEY_256 32
21enum qcedev_oper_enum {
22 QCEDEV_OPER_DEC = 0,
23 QCEDEV_OPER_ENC = 1,
24 QCEDEV_OPER_DEC_NO_KEY = 2,
25 QCEDEV_OPER_ENC_NO_KEY = 3,
26 QCEDEV_OPER_LAST
27};
28
29enum qcedev_cipher_alg_enum {
30 QCEDEV_ALG_DES = 0,
31 QCEDEV_ALG_3DES = 1,
32 QCEDEV_ALG_AES = 2,
33 QCEDEV_ALG_LAST
34};
35
36enum qcedev_cipher_mode_enum {
37 QCEDEV_AES_MODE_CBC = 0,
38 QCEDEV_AES_MODE_ECB = 1,
39 QCEDEV_AES_MODE_CTR = 2,
40 QCEDEV_AES_MODE_XTS = 3,
41 QCEDEV_AES_MODE_CCM = 4,
42 QCEDEV_DES_MODE_CBC = 5,
43 QCEDEV_DES_MODE_ECB = 6,
44 QCEDEV_AES_DES_MODE_LAST
45};
46
47enum qcedev_sha_alg_enum {
48 QCEDEV_ALG_SHA1 = 0,
49 QCEDEV_ALG_SHA256 = 1,
50 QCEDEV_ALG_SHA1_HMAC = 2,
51 QCEDEV_ALG_SHA256_HMAC = 3,
52 QCEDEV_ALG_AES_CMAC = 4,
53 QCEDEV_ALG_SHA_ALG_LAST
54};
55
56struct buf_info {
57 union {
58 uint32_t offset;
59 uint8_t *vaddr;
60 };
61 uint32_t len;
62};
63
64struct qcedev_vbuf_info {
65 struct buf_info src[QCEDEV_MAX_BUFFERS];
66 struct buf_info dst[QCEDEV_MAX_BUFFERS];
67};
68
69struct qcedev_pmem_info {
70 int fd_src;
71 struct buf_info src[QCEDEV_MAX_BUFFERS];
72 int fd_dst;
73 struct buf_info dst[QCEDEV_MAX_BUFFERS];
74};
75
76struct qcedev_cipher_op_req {
77 uint8_t use_pmem;
78 union {
79 struct qcedev_pmem_info pmem;
80 struct qcedev_vbuf_info vbuf;
81 };
82 uint32_t entries;
83 uint32_t data_len;
84 uint8_t in_place_op;
85 uint8_t enckey[QCEDEV_MAX_KEY_SIZE];
86 uint32_t encklen;
87 uint8_t iv[QCEDEV_MAX_IV_SIZE];
88 uint32_t ivlen;
89 uint32_t byteoffset;
90 enum qcedev_cipher_alg_enum alg;
91 enum qcedev_cipher_mode_enum mode;
92 enum qcedev_oper_enum op;
93};
94
95struct qcedev_sha_op_req {
96 struct buf_info data[QCEDEV_MAX_BUFFERS];
97 uint32_t entries;
98 uint32_t data_len;
99 uint8_t digest[QCEDEV_MAX_SHA_DIGEST];
100 uint32_t diglen;
101 uint8_t *authkey;
102 uint32_t authklen;
103 enum qcedev_sha_alg_enum alg;
104};
105
106
107#define QCEDEV_IOC_MAGIC 0x87
108
109#define QCEDEV_IOCTL_ENC_REQ \
110 _IOWR(QCEDEV_IOC_MAGIC, 1, struct qcedev_cipher_op_req)
111#define QCEDEV_IOCTL_DEC_REQ \
112 _IOWR(QCEDEV_IOC_MAGIC, 2, struct qcedev_cipher_op_req)
113#define QCEDEV_IOCTL_SHA_INIT_REQ \
114 _IOWR(QCEDEV_IOC_MAGIC, 3, struct qcedev_sha_op_req)
115#define QCEDEV_IOCTL_SHA_UPDATE_REQ \
116 _IOWR(QCEDEV_IOC_MAGIC, 4, struct qcedev_sha_op_req)
117#define QCEDEV_IOCTL_SHA_FINAL_REQ \
118 _IOWR(QCEDEV_IOC_MAGIC, 5, struct qcedev_sha_op_req)
119#define QCEDEV_IOCTL_GET_SHA_REQ \
120 _IOWR(QCEDEV_IOC_MAGIC, 6, struct qcedev_sha_op_req)
121#define QCEDEV_IOCTL_LOCK_CE \
122 _IO(QCEDEV_IOC_MAGIC, 7)
123#define QCEDEV_IOCTL_UNLOCK_CE \
124 _IO(QCEDEV_IOC_MAGIC, 8)
125#define QCEDEV_IOCTL_GET_CMAC_REQ \
126 _IOWR(QCEDEV_IOC_MAGIC, 9, struct qcedev_cipher_op_req)
127#endif