mmc: msm_sdcc: Poll for TX/RX active bits after data transfer
In newer SDCC v4 versions, the internal single port RAM is
replaced by dual-Port RAM which requires clock muxing after
RX transactions. To ensure clock switch is completed
successfully, the driver has to poll for TX/RX active bits
de-assertion in status register before initiating new transaction.
Change-Id: Idcd7732fa4fa490017e69d62535dbff6eb335eb6
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index cc41c46..3b1dbc7 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -412,6 +412,7 @@
struct mutex clk_mutex;
bool pending_resume;
unsigned int idle_tout_ms; /* Timeout in msecs */
+ bool pending_dpsm_reset;
struct msmsdcc_msm_bus_vote msm_bus_vote;
struct device_attribute max_bus_bw;
struct device_attribute polling;
@@ -426,6 +427,7 @@
#define MSMSDCC_REG_WR_ACTIVE (1 << 4)
#define MSMSDCC_SW_RST (1 << 5)
#define MSMSDCC_SW_RST_CFG (1 << 6)
+#define MSMSDCC_WAIT_FOR_TX_RX (1 << 7)
#define set_hw_caps(h, val) ((h)->hw_caps |= val)
#define is_sps_mode(h) ((h)->hw_caps & MSMSDCC_SPS_BAM_SUP)
@@ -435,6 +437,7 @@
#define is_wait_for_reg_write(h) ((h)->hw_caps & MSMSDCC_REG_WR_ACTIVE)
#define is_sw_hard_reset(h) ((h)->hw_caps & MSMSDCC_SW_RST)
#define is_sw_reset_save_config(h) ((h)->hw_caps & MSMSDCC_SW_RST_CFG)
+#define is_wait_for_tx_rx_active(h) ((h)->hw_caps & MSMSDCC_WAIT_FOR_TX_RX)
/* Set controller capabilities based on version */
static inline void set_default_hw_caps(struct msmsdcc_host *host)
@@ -453,7 +456,8 @@
version &= MSMSDCC_VERSION_MASK;
if (version) /* SDCC v4 and greater */
host->hw_caps |= MSMSDCC_AUTO_PROG_DONE |
- MSMSDCC_SOFT_RESET | MSMSDCC_REG_WR_ACTIVE;
+ MSMSDCC_SOFT_RESET | MSMSDCC_REG_WR_ACTIVE
+ | MSMSDCC_WAIT_FOR_TX_RX;
if (version >= 0x2D) /* SDCC v4 2.1.0 and greater */
host->hw_caps |= MSMSDCC_SW_RST | MSMSDCC_SW_RST_CFG;