msm_fb: display: fix dsi pll setting to reduce phase lock time
Sometimes, it may take up to 8 ms to have dsi PLL phase locked.
Set dsi pll optimal values at PLL_CTRL registers 16 and 17 to
reduce the PLL phase lock time.
CRs-fixed: 468455
Change-Id: I1a6c57e6599052e1864de55cc8d57326b1c367e0
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-8930-display.c b/arch/arm/mach-msm/board-8930-display.c
index a7ba04a..8d78570 100644
--- a/arch/arm/mach-msm/board-8930-display.c
+++ b/arch/arm/mach-msm/board-8930-display.c
@@ -492,7 +492,7 @@
/* pll control */
{0x0, 0xe, 0x30, 0xda, 0x00, 0x10, 0x0f, 0x61,
0x40, 0x07, 0x03,
- 0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x02},
+ 0x00, 0x1a, 0x00, 0x00, 0x02, 0x0e, 0x01, 0x00, 0x02},
};
static struct mipi_dsi_panel_platform_data novatek_pdata = {