msm: clock-local: Cleanup function naming conventions
Rename the family of functions with the 'local_clk' prefix to
have an 'rcg_clk' prefix instead, so that the function names
matche the type of clock (and type of struct) those functions
operate on.
This also helps to disambiguate these functions from other
functions that operate on different types of "local clocks"
(ie. branches, PLLs, etc).
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-7x30.c b/arch/arm/mach-msm/clock-7x30.c
index d42db8a..44b8798 100644
--- a/arch/arm/mach-msm/clock-7x30.c
+++ b/arch/arm/mach-msm/clock-7x30.c
@@ -2965,20 +2965,20 @@
* Clock operation handler registration
*/
static struct clk_ops soc_clk_ops_7x30 = {
- .enable = local_clk_enable,
- .disable = local_clk_disable,
- .auto_off = local_clk_auto_off,
- .set_rate = local_clk_set_rate,
- .set_min_rate = local_clk_set_min_rate,
- .set_max_rate = local_clk_set_max_rate,
- .get_rate = local_clk_get_rate,
- .list_rate = local_clk_list_rate,
- .is_enabled = local_clk_is_enabled,
- .round_rate = local_clk_round_rate,
+ .enable = rcg_clk_enable,
+ .disable = rcg_clk_disable,
+ .auto_off = rcg_clk_auto_off,
+ .set_rate = rcg_clk_set_rate,
+ .set_min_rate = rcg_clk_set_min_rate,
+ .set_max_rate = rcg_clk_set_max_rate,
+ .get_rate = rcg_clk_get_rate,
+ .list_rate = rcg_clk_list_rate,
+ .is_enabled = rcg_clk_is_enabled,
+ .round_rate = rcg_clk_round_rate,
.reset = msm7x30_clk_reset,
.set_flags = soc_clk_set_flags,
.is_local = local_clk_is_local,
- .get_parent = local_clk_get_parent,
+ .get_parent = rcg_clk_get_parent,
};
static struct clk_ops clk_ops_branch = {
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index e205440..b792702 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -431,19 +431,19 @@
}
static struct clk_ops soc_clk_ops_8960 = {
- .enable = local_clk_enable,
- .disable = local_clk_disable,
- .auto_off = local_clk_auto_off,
- .set_rate = local_clk_set_rate,
- .set_min_rate = local_clk_set_min_rate,
- .set_max_rate = local_clk_set_max_rate,
- .get_rate = local_clk_get_rate,
- .list_rate = local_clk_list_rate,
- .is_enabled = local_clk_is_enabled,
- .round_rate = local_clk_round_rate,
+ .enable = rcg_clk_enable,
+ .disable = rcg_clk_disable,
+ .auto_off = rcg_clk_auto_off,
+ .set_rate = rcg_clk_set_rate,
+ .set_min_rate = rcg_clk_set_min_rate,
+ .set_max_rate = rcg_clk_set_max_rate,
+ .get_rate = rcg_clk_get_rate,
+ .list_rate = rcg_clk_list_rate,
+ .is_enabled = rcg_clk_is_enabled,
+ .round_rate = rcg_clk_round_rate,
.reset = soc_clk_reset,
.is_local = local_clk_is_local,
- .get_parent = local_clk_get_parent,
+ .get_parent = rcg_clk_get_parent,
};
static struct clk_ops clk_ops_branch = {
@@ -4110,10 +4110,10 @@
* The halt status bits for PDM and TSSC may be incorrect at boot.
* Toggle these clocks on and off to refresh them.
*/
- local_clk_enable(&pdm_clk.c);
- local_clk_disable(&pdm_clk.c);
- local_clk_enable(&tssc_clk.c);
- local_clk_disable(&tssc_clk.c);
+ rcg_clk_enable(&pdm_clk.c);
+ rcg_clk_disable(&pdm_clk.c);
+ rcg_clk_enable(&tssc_clk.c);
+ rcg_clk_disable(&tssc_clk.c);
if (machine_is_msm8960_sim()) {
clk_set_rate(&sdc1_clk.c, 48000000);
diff --git a/arch/arm/mach-msm/clock-8x60.c b/arch/arm/mach-msm/clock-8x60.c
index f51cf88..bf7397e 100644
--- a/arch/arm/mach-msm/clock-8x60.c
+++ b/arch/arm/mach-msm/clock-8x60.c
@@ -518,19 +518,19 @@
}
static struct clk_ops soc_clk_ops_8x60 = {
- .enable = local_clk_enable,
- .disable = local_clk_disable,
- .auto_off = local_clk_auto_off,
- .set_rate = local_clk_set_rate,
- .set_min_rate = local_clk_set_min_rate,
- .set_max_rate = local_clk_set_max_rate,
- .get_rate = local_clk_get_rate,
- .list_rate = local_clk_list_rate,
- .is_enabled = local_clk_is_enabled,
- .round_rate = local_clk_round_rate,
+ .enable = rcg_clk_enable,
+ .disable = rcg_clk_disable,
+ .auto_off = rcg_clk_auto_off,
+ .set_rate = rcg_clk_set_rate,
+ .set_min_rate = rcg_clk_set_min_rate,
+ .set_max_rate = rcg_clk_set_max_rate,
+ .get_rate = rcg_clk_get_rate,
+ .list_rate = rcg_clk_list_rate,
+ .is_enabled = rcg_clk_is_enabled,
+ .round_rate = rcg_clk_round_rate,
.reset = soc_clk_reset,
.is_local = local_clk_is_local,
- .get_parent = local_clk_get_parent,
+ .get_parent = rcg_clk_get_parent,
};
static struct clk_ops clk_ops_branch = {
@@ -3789,10 +3789,10 @@
/* The halt status bits for PDM and TSSC may be incorrect at boot.
* Toggle these clocks on and off to refresh them. */
- local_clk_enable(&pdm_clk.c);
- local_clk_disable(&pdm_clk.c);
- local_clk_enable(&tssc_clk.c);
- local_clk_disable(&tssc_clk.c);
+ rcg_clk_enable(&pdm_clk.c);
+ rcg_clk_disable(&pdm_clk.c);
+ rcg_clk_enable(&tssc_clk.c);
+ rcg_clk_disable(&tssc_clk.c);
msm_clock_init(msm_clocks_8x60, ARRAY_SIZE(msm_clocks_8x60));
}
diff --git a/arch/arm/mach-msm/clock-local.c b/arch/arm/mach-msm/clock-local.c
index 17f00d8..95a1e71 100644
--- a/arch/arm/mach-msm/clock-local.c
+++ b/arch/arm/mach-msm/clock-local.c
@@ -386,7 +386,7 @@
}
/* Perform any register operations required to enable the clock. */
-static void __local_clk_enable_reg(struct rcg_clk *clk)
+static void __rcg_clk_enable_reg(struct rcg_clk *clk)
{
u32 reg_val;
void __iomem *const reg = clk->b.ctl_reg;
@@ -458,7 +458,7 @@
}
/* Perform any register operations required to disable the generator. */
-static void __local_clk_disable_reg(struct rcg_clk *clk)
+static void __rcg_clk_disable_reg(struct rcg_clk *clk)
{
void __iomem *const reg = clk->b.ctl_reg;
uint32_t reg_val;
@@ -486,30 +486,30 @@
}
}
-static int _local_clk_enable(struct rcg_clk *clk)
+static int _rcg_clk_enable(struct rcg_clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&local_clock_reg_lock, flags);
- __local_clk_enable_reg(clk);
+ __rcg_clk_enable_reg(clk);
clk->enabled = true;
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
return 0;
}
-static void _local_clk_disable(struct rcg_clk *clk)
+static void _rcg_clk_disable(struct rcg_clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&local_clock_reg_lock, flags);
- __local_clk_disable_reg(clk);
+ __rcg_clk_disable_reg(clk);
clk->enabled = false;
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
/* Enable a clock and any related power rail. */
-int local_clk_enable(struct clk *c)
+int rcg_clk_enable(struct clk *c)
{
int rc;
struct rcg_clk *clk = to_rcg_clk(c);
@@ -520,7 +520,7 @@
rc = clk_enable(clk->depends);
if (rc)
goto err_dep;
- rc = _local_clk_enable(clk);
+ rc = _rcg_clk_enable(clk);
if (rc)
goto err_enable;
return rc;
@@ -534,19 +534,19 @@
}
/* Disable a clock and any related power rail. */
-void local_clk_disable(struct clk *c)
+void rcg_clk_disable(struct clk *c)
{
struct rcg_clk *clk = to_rcg_clk(c);
- _local_clk_disable(clk);
+ _rcg_clk_disable(clk);
clk_disable(clk->depends);
local_unvote_sys_vdd(clk->current_freq->sys_vdd);
}
/* Turn off a clock at boot, without checking refcounts or disabling depends. */
-void local_clk_auto_off(struct clk *c)
+void rcg_clk_auto_off(struct clk *c)
{
- _local_clk_disable(to_rcg_clk(c));
+ _rcg_clk_disable(to_rcg_clk(c));
}
/*
@@ -554,7 +554,7 @@
*/
/* Set a clock's frequency. */
-static int _local_clk_set_rate(struct rcg_clk *clk, struct clk_freq_tbl *nf)
+static int _rcg_clk_set_rate(struct rcg_clk *clk, struct clk_freq_tbl *nf)
{
struct clk_freq_tbl *cf;
int rc = 0;
@@ -596,7 +596,7 @@
__branch_clk_disable_reg(&x->b, x->c.dbg_name);
}
if (clk->enabled)
- __local_clk_disable_reg(clk);
+ __rcg_clk_disable_reg(clk);
}
/* Perform clock-specific frequency switch operations. */
@@ -604,7 +604,7 @@
clk->set_rate(clk, nf);
/*
- * Current freq must be updated before __local_clk_enable_reg()
+ * Current freq must be updated before __rcg_clk_enable_reg()
* is called to make sure the MNCNTR_EN bit is set correctly.
*/
clk->current_freq = nf;
@@ -612,7 +612,7 @@
/* Enable any clocks that were disabled. */
if (clk->bank_masks == NULL) {
if (clk->enabled)
- __local_clk_enable_reg(clk);
+ __rcg_clk_enable_reg(clk);
/* Enable only branches that were ON before. */
list_for_each_entry(chld, &clk->c.children, siblings) {
struct branch_clk *x = to_branch_clk(chld);
@@ -635,7 +635,7 @@
}
/* Set a clock to an exact rate. */
-int local_clk_set_rate(struct clk *c, unsigned rate)
+int rcg_clk_set_rate(struct clk *c, unsigned rate)
{
struct rcg_clk *clk = to_rcg_clk(c);
struct clk_freq_tbl *nf;
@@ -647,11 +647,11 @@
if (nf->freq_hz == FREQ_END)
return -EINVAL;
- return _local_clk_set_rate(clk, nf);
+ return _rcg_clk_set_rate(clk, nf);
}
/* Set a clock to a rate greater than some minimum. */
-int local_clk_set_min_rate(struct clk *c, unsigned rate)
+int rcg_clk_set_min_rate(struct clk *c, unsigned rate)
{
struct rcg_clk *clk = to_rcg_clk(c);
struct clk_freq_tbl *nf;
@@ -663,17 +663,17 @@
if (nf->freq_hz == FREQ_END)
return -EINVAL;
- return _local_clk_set_rate(clk, nf);
+ return _rcg_clk_set_rate(clk, nf);
}
/* Set a clock to a maximum rate. */
-int local_clk_set_max_rate(struct clk *clk, unsigned rate)
+int rcg_clk_set_max_rate(struct clk *clk, unsigned rate)
{
return -EPERM;
}
/* Get the currently-set rate of a clock in Hz. */
-unsigned local_clk_get_rate(struct clk *c)
+unsigned rcg_clk_get_rate(struct clk *c)
{
struct rcg_clk *clk = to_rcg_clk(c);
unsigned long flags;
@@ -694,13 +694,13 @@
}
/* Check if a clock is currently enabled. */
-int local_clk_is_enabled(struct clk *clk)
+int rcg_clk_is_enabled(struct clk *clk)
{
return to_rcg_clk(clk)->enabled;
}
/* Return a supported rate that's at least the specified rate. */
-long local_clk_round_rate(struct clk *c, unsigned rate)
+long rcg_clk_round_rate(struct clk *c, unsigned rate)
{
struct rcg_clk *clk = to_rcg_clk(c);
struct clk_freq_tbl *f;
@@ -718,7 +718,7 @@
}
/* Return the nth supported frequency for a given clock. */
-int local_clk_list_rate(struct clk *c, unsigned n)
+int rcg_clk_list_rate(struct clk *c, unsigned n)
{
struct rcg_clk *clk = to_rcg_clk(c);
@@ -728,7 +728,7 @@
return (clk->freq_tbl + n)->freq_hz;
}
-struct clk *local_clk_get_parent(struct clk *clk)
+struct clk *rcg_clk_get_parent(struct clk *clk)
{
return to_rcg_clk(clk)->current_freq->src_clk;
}
diff --git a/arch/arm/mach-msm/clock-local.h b/arch/arm/mach-msm/clock-local.h
index e465e08..58c76e9 100644
--- a/arch/arm/mach-msm/clock-local.h
+++ b/arch/arm/mach-msm/clock-local.h
@@ -142,6 +142,18 @@
return container_of(clk, struct rcg_clk, c);
}
+int rcg_clk_enable(struct clk *clk);
+void rcg_clk_disable(struct clk *clk);
+void rcg_clk_auto_off(struct clk *clk);
+int rcg_clk_set_rate(struct clk *clk, unsigned rate);
+int rcg_clk_set_min_rate(struct clk *clk, unsigned rate);
+int rcg_clk_set_max_rate(struct clk *clk, unsigned rate);
+unsigned rcg_clk_get_rate(struct clk *clk);
+int rcg_clk_list_rate(struct clk *clk, unsigned n);
+int rcg_clk_is_enabled(struct clk *clk);
+long rcg_clk_round_rate(struct clk *clk, unsigned rate);
+struct clk *rcg_clk_get_parent(struct clk *c);
+
/*
* SYS_VDD voltage levels
*/
@@ -288,22 +300,7 @@
*/
int local_vote_sys_vdd(enum sys_vdd_level level);
int local_unvote_sys_vdd(enum sys_vdd_level level);
-
-/*
- * clk_ops APIs
- */
-int local_clk_enable(struct clk *clk);
-void local_clk_disable(struct clk *clk);
-void local_clk_auto_off(struct clk *clk);
-int local_clk_set_rate(struct clk *clk, unsigned rate);
-int local_clk_set_min_rate(struct clk *clk, unsigned rate);
-int local_clk_set_max_rate(struct clk *clk, unsigned rate);
-unsigned local_clk_get_rate(struct clk *clk);
-int local_clk_list_rate(struct clk *clk, unsigned n);
-int local_clk_is_enabled(struct clk *clk);
-long local_clk_round_rate(struct clk *clk, unsigned rate);
bool local_clk_is_local(struct clk *clk);
-struct clk *local_clk_get_parent(struct clk *c);
/*
* Required SoC-specific functions, implemented for every supported SoC