commit 06a2c720d2ffc2a3ea5406c881943aeb0a0b91b7
author Rajeev Kulkarni <krajeev@codeaurora.org> Fri Jul 06 16:47:16 2012 -0700
committer Jordan Crouse <jcrouse@codeaurora.org> Wed Jul 11 10:49:59 2012 -0600
tree 2bce4c393397ff4363903c2aeab005227a9756f9
parent 6757fbad262ce79a7ffaa805bdf6700306adad9c

msm:kgsl: Adjust the GMEM save Procedure as per A3XX GPU spec

Modify GMEM Save procedure as per A3XX GPU spec to support
multiple GPU revisions. It also fixes A3XX GPU
hang caused by GMEM save procedure.

CRs-Fixed: 375034
Change-Id: I24a4d6c4fd8304b3f41a167c116a75f2e3680158
Signed-off-by: Rajeev Kulkarni <krajeev@codeaurora.org>

drivers/gpu/msm/a3xx_reg.h

diff --git a/drivers/gpu/msm/a3xx_reg.h b/drivers/gpu/msm/a3xx_reg.h
index f5ee1d7..2e8964d 100644
--- a/drivers/gpu/msm/a3xx_reg.h
+++ b/drivers/gpu/msm/a3xx_reg.h
@@ -151,6 +151,7 @@
 #define A3XX_GRAS_CL_USER_PLANE_Y5 0xCB5
 #define A3XX_GRAS_CL_USER_PLANE_Z5 0xCB6
 #define A3XX_GRAS_CL_USER_PLANE_W5 0xCB7
+#define A3XX_VFD_PERFCOUNTER0_SELECT 0xE44
 #define A3XX_VPC_VPC_DEBUG_RAM_SEL 0xE61
 #define A3XX_VPC_VPC_DEBUG_RAM_READ 0xE62
 #define A3XX_UCHE_CACHE_INVALIDATE0_REG 0xEA0
@@ -396,6 +397,7 @@
 #define RB_STENCILCONTROL_STENCIL_ZPASS 14
 #define RB_STENCILCONTROL_STENCIL_ZPASS_BF 26
 #define SP_FSCTRLREG0_FSFULLREGFOOTPRINT 10
+#define SP_FSCTRLREG0_FSHALFREGFOOTPRINT 4
 #define SP_FSCTRLREG0_FSICACHEINVALID 2
 #define SP_FSCTRLREG0_FSINOUTREGOVERLAP 18
 #define SP_FSCTRLREG0_FSINSTRBUFFERMODE 1
@@ -408,13 +410,16 @@
 #define SP_FSCTRLREG1_FSINITIALOUTSTANDING 20
 #define SP_FSCTRLREG1_HALFPRECVAROFFSET 24
 #define SP_FSMRTREG_REGID 0
+#define SP_FSMRTREG_PRECISION 8
 #define SP_FSOUTREG_PAD0 2
 #define SP_IMAGEOUTPUTREG_MRTFORMAT 0
+#define SP_IMAGEOUTPUTREG_DEPTHOUTMODE 3
 #define SP_IMAGEOUTPUTREG_PAD0 6
 #define SP_OBJOFFSETREG_CONSTOBJECTSTARTOFFSET 16
 #define SP_OBJOFFSETREG_SHADEROBJOFFSETINIC 25
 #define SP_SHADERLENGTH_LEN 0
 #define SP_SPCTRLREG_CONSTMODE 18
+#define SP_SPCTRLREG_LOMODE 22
 #define SP_SPCTRLREG_SLEEPMODE 20
 #define SP_VSCTRLREG0_VSFULLREGFOOTPRINT 10
 #define SP_VSCTRLREG0_VSICACHEINVALID 2
@@ -455,6 +460,7 @@
 #define VFD_FETCHINSTRUCTIONS_STEPRATE 24
 #define VFD_FETCHINSTRUCTIONS_SWITCHNEXT 17
 #define VFD_THREADINGTHRESHOLD_REGID_VTXCNT 8
+#define VFD_THREADINGTHRESHOLD_REGID_THRESHOLD 0
 #define VFD_THREADINGTHRESHOLD_RESERVED6 4
 #define VPC_VPCATTR_LMSIZE 28
 #define VPC_VPCATTR_THRHDASSIGN 12