msm-fb: display: mdp clock scaling clean up
clean up of clock scaling code to organize it better
Signed-off-by: Nagamalleswararao Ganji <nganji@codeaurora.org>
diff --git a/drivers/video/msm/mdp.c b/drivers/video/msm/mdp.c
index 586d97f..1339e17 100644
--- a/drivers/video/msm/mdp.c
+++ b/drivers/video/msm/mdp.c
@@ -1140,8 +1140,6 @@
printk(KERN_ERR "%s invalid perf level\n", __func__);
else {
mutex_lock(&mdp_clk_lock);
- if (mdp4_extn_disp)
- perf_level = 1;
ret = clk_set_rate(mdp_clk,
mdp_pdata->
mdp_core_clk_table[mdp_pdata->num_mdp_clk
@@ -1177,8 +1175,6 @@
printk(KERN_ERR "%s invalid perf level\n", __func__);
clk_rate = mdp_get_core_clk();
} else {
- if (mdp4_extn_disp)
- perf_level = 1;
clk_rate = mdp_pdata->
mdp_core_clk_table[mdp_pdata->num_mdp_clk
- perf_level];
diff --git a/drivers/video/msm/mdp4.h b/drivers/video/msm/mdp4.h
index 0b905f9..57eae4e 100644
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -35,6 +35,13 @@
#define MDP4_RGB_BASE 0x40000
#define MDP4_RGB_OFF 0x10000
+enum {
+ OVERLAY_PERF_LEVEL1 = 1,
+ OVERLAY_PERF_LEVEL2,
+ OVERLAY_PERF_LEVEL3,
+ OVERLAY_PERF_LEVEL4
+};
+
enum mdp4_overlay_status {
MDP4_OVERLAY_TYPE_UNSET,
MDP4_OVERLAY_TYPE_SET,
@@ -469,7 +476,7 @@
void mdp4_overlay_lcdc_wait4vsync(struct msm_fb_data_type *mfd);
void mdp4_overlay_lcdc_vsync_push(struct msm_fb_data_type *mfd,
struct mdp4_overlay_pipe *pipe);
-
+void mdp4_update_perf_level(u32 perf_level);
void mdp4_set_perf_level(void);
void mdp4_mddi_overlay_dmas_restore(void);
diff --git a/drivers/video/msm/mdp4_dtv.c b/drivers/video/msm/mdp4_dtv.c
index d9550fc..f07a8b4 100644
--- a/drivers/video/msm/mdp4_dtv.c
+++ b/drivers/video/msm/mdp4_dtv.c
@@ -126,7 +126,6 @@
pm_qos_rate = panel_pixclock_freq / 1000 ;
else
pm_qos_rate = 58000;
- mdp_set_core_clk(1);
mdp4_extn_disp = 1;
#ifdef CONFIG_MSM_BUS_SCALING
if (dtv_bus_scale_handle > 0)
diff --git a/drivers/video/msm/mdp4_overlay.c b/drivers/video/msm/mdp4_overlay.c
index 0f4d330..831a16b 100644
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -99,6 +99,7 @@
static struct mdp4_overlay_ctrl *ctrl = &mdp4_overlay_db;
static int new_perf_level;
+
/* static array with index 0 for unset status and 1 for set status */
static bool overlay_status[MDP4_OVERLAY_TYPE_MAX];
@@ -1896,10 +1897,6 @@
#define OVERLAY_VGA_SIZE 0x04B000
#define OVERLAY_720P_TILE_SIZE 0x0E6000
#define OVERLAY_WSVGA_SIZE 0x98000 /* 1024x608, align 600 to 32bit */
-#define OVERLAY_PERF_LEVEL1 1
-#define OVERLAY_PERF_LEVEL2 2
-#define OVERLAY_PERF_LEVEL3 3
-#define OVERLAY_PERF_LEVEL4 4
#ifdef CONFIG_MSM_BUS_SCALING
#define OVERLAY_BUS_SCALE_TABLE_BASE 6
@@ -1929,6 +1926,9 @@
if (req->is_fg && ((req->alpha & 0x0ff) == 0xff))
is_fg = 1;
+ if (mdp4_extn_disp)
+ return OVERLAY_PERF_LEVEL1;
+
if (req->flags & MDP_DEINTERLACE)
return OVERLAY_PERF_LEVEL1;
@@ -1950,13 +1950,24 @@
return OVERLAY_PERF_LEVEL1;
}
+void mdp4_update_perf_level(u32 perf_level)
+{
+ new_perf_level = perf_level;
+}
+
void mdp4_set_perf_level(void)
{
static int old_perf_level;
+ int cur_perf_level;
- if (old_perf_level != new_perf_level) {
- mdp_set_core_clk(new_perf_level);
- old_perf_level = new_perf_level;
+ if (mdp4_extn_disp)
+ cur_perf_level = OVERLAY_PERF_LEVEL1;
+ else
+ cur_perf_level = new_perf_level;
+
+ if (old_perf_level != cur_perf_level) {
+ mdp_set_core_clk(cur_perf_level);
+ old_perf_level = cur_perf_level;
}
}
@@ -2046,9 +2057,8 @@
mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, true);
}
-
if (new_perf_level != perf_level) {
- new_perf_level = perf_level;
+ mdp4_update_perf_level(perf_level);
/* change clck base on perf level */
flags = pipe->flags;
@@ -2175,7 +2185,7 @@
if (!(ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt +
ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt))
- new_perf_level = OVERLAY_PERF_LEVEL4;
+ mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
mutex_unlock(&mfd->dma->ov_mutex);
diff --git a/drivers/video/msm/mdp4_util.c b/drivers/video/msm/mdp4_util.c
index 77b0008..438cce5 100644
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -246,6 +246,8 @@
/* MDP cmd block enable */
mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
+ mdp4_update_perf_level(OVERLAY_PERF_LEVEL4);
+
#ifdef MDP4_ERROR
/*
* Issue software reset on DMA_P will casue DMA_P dma engine stall
diff --git a/drivers/video/msm/mdp_hw40.c b/drivers/video/msm/mdp_hw40.c
index d36125e..a642c9b 100644
--- a/drivers/video/msm/mdp_hw40.c
+++ b/drivers/video/msm/mdp_hw40.c
@@ -68,7 +68,7 @@
/* XXX: why set this? QCT says it should be > mdp_pclk,
* but they never set the clkrate of pclk */
- mdp_set_core_clk(4);
+ clk_set_rate(mdp->clk, 122880000); /* 122.88 Mhz */
pr_info("%s: mdp_clk=%lu\n", __func__, clk_get_rate(mdp->clk));
/* TODO: Configure the VG/RGB pipes fetch data */
diff --git a/drivers/video/msm/tvenc.c b/drivers/video/msm/tvenc.c
index cdf3823..672b2a7 100644
--- a/drivers/video/msm/tvenc.c
+++ b/drivers/video/msm/tvenc.c
@@ -222,7 +222,6 @@
if (mfd->ebi1_clk)
clk_enable(mfd->ebi1_clk);
#endif
- mdp_set_core_clk(1);
mdp4_extn_disp = 1;
if (tvenc_pdata && tvenc_pdata->pm_vid_en)
ret = tvenc_pdata->pm_vid_en(1);