)]}'
{
  "commit": "08357f82d4decc48bbfd39ae30d5fe0754f7f576",
  "tree": "c8516a8f208e1cb253bd33f41857b0699104b130",
  "parents": [
    "60a762b6a6dec17cc4339b60154902fd04c2f9f2"
  ],
  "author": {
    "name": "Zoltan Menyhart",
    "email": "Zoltan.Menyhart@bull.net",
    "time": "Fri Jun 03 05:36:00 2005 -0700"
  },
  "committer": {
    "name": "Tony Luck",
    "email": "tony.luck@intel.com",
    "time": "Tue Jul 12 15:33:18 2005 -0700"
  },
  "message": "[IA64] improve flush_icache_range()\n\nCheck with PAL to see what the i-cache line size is for\neach level of the cache, and so use the correct stride\nwhen flushing the cache.\n\nAcked-by: David Mosberger\nSigned-off-by: Tony Luck \u003ctony.luck@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2693e1522d7cc45184e4b8b2e50819cdd2020cb1",
      "old_mode": 33188,
      "old_path": "arch/ia64/kernel/setup.c",
      "new_id": "7fc891aca4460859ece27cc234bba099ad372443",
      "new_mode": 33188,
      "new_path": "arch/ia64/kernel/setup.c"
    },
    {
      "type": "modify",
      "old_id": "a1af9146cfdbea5fa0530f8a3f68afd0fad70094",
      "old_mode": 33188,
      "old_path": "arch/ia64/lib/flush.S",
      "new_id": "3e2cfa2c6d39436d29f0c05e8f8cb1611fe76560",
      "new_mode": 33188,
      "new_path": "arch/ia64/lib/flush.S"
    }
  ]
}