)]}'
{
  "commit": "09bfeea13cea843fb03eaa96b5d891fa0abdcc90",
  "tree": "83777d26c3029d373d67f61f6d08884ae275cea3",
  "parents": [
    "a8d6829044901a67732904be5f1eacdf8539604f"
  ],
  "author": {
    "name": "Andreas Herrmann",
    "email": "andreas.herrmann3@amd.com",
    "time": "Thu Sep 18 21:12:10 2008 +0200"
  },
  "committer": {
    "name": "Thomas Gleixner",
    "email": "tglx@linutronix.de",
    "time": "Tue Sep 23 11:38:53 2008 +0200"
  },
  "message": "x86: c1e_idle: don\u0027t mark TSC unstable if CPU has invariant TSC\n\nImpact: Functional TSC is marked unstable on AMD family 0x10 and 0x11 CPUs.\n\nThis would be wrong because for those CPUs \"invariant TSC\" means:\n\n   \"The TSC counts at the same rate in all P-states, all C states, S0,\n   or S1\"\n\n(See \"Processor BIOS and Kernel Developer\u0027s Guides\" for those CPUs.)\n\n[ tglx: Changed C1E to AMD C1E in the printks to avoid confusion \n\twith Intel C1E ]\n\nSigned-off-by: Andreas Herrmann \u003candreas.herrmann3@amd.com\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\n\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d8c2a299bfe51d774d3ce4e9027dc02b1ceb7472",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/process.c",
      "new_id": "876e91890777ae9758e5efcb7dc72075a26e341e",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/process.c"
    }
  ]
}