)]}'
{
  "commit": "0b2c3afdaaaa3e577300b2235df43eb8af00020b",
  "tree": "a19e12791a9d109f61f1edce731f50589302d04d",
  "parents": [
    "70e137eb48f62e59dfa5e06d0d01f123e9464f9a"
  ],
  "author": {
    "name": "Chris Zankel",
    "email": "chris@zankel.net",
    "time": "Tue Feb 12 10:11:45 2008 -0800"
  },
  "committer": {
    "name": "Chris Zankel",
    "email": "chris@zankel.net",
    "time": "Wed Feb 13 17:08:18 2008 -0800"
  },
  "message": "[XTENSA] Fix icache flush for cache aliasing\n\nSet the execution bit in the temporary TLB when we flush the\ninstruction cache.\n\nSigned-off-by: Chris Zankel \u003cchris@zankel.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e1f880368e3276e5eaaaa395530e1f457ac0008c",
      "old_mode": 33188,
      "old_path": "arch/xtensa/mm/misc.S",
      "new_id": "c885664211d15ffea236ae0fc4fe32c61d7a1155",
      "new_mode": 33188,
      "new_path": "arch/xtensa/mm/misc.S"
    }
  ]
}