commit 0e0486f251b6e21d56298923bc41ed58d25678f7
author Jordan Crouse <jcrouse@codeaurora.org> Thu Jul 28 08:37:58 2011 -0600
committer Bryan Huntsman <bryanh@codeaurora.org> Mon Oct 03 10:28:29 2011 -0700
tree 445c8c052ec4c39d73f3c829ebf2c5a18bb959c5
parent c8c9fcd258b9c6c7ee1f4ad33fe50215d5f40b16

msm: kgsl: Rearrange some drawctxt functions

Move some of the drawctxt functions that are common
to A2XX and A3XX back to the generic drawctxt code
and headers.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

drivers/gpu/msm/adreno_ringbuffer.c

diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index 892012c..1d44d20 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -361,21 +361,21 @@
 	GSL_RB_WRITE(cmds, cmds_gpu, 0x00000000);
 
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO));
+		SUBBLOCK_OFFSET(REG_RB_SURFACE_INFO));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET));
+		SUBBLOCK_OFFSET(REG_PA_SC_WINDOW_OFFSET));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX));
+		SUBBLOCK_OFFSET(REG_VGT_MAX_VTX_INDX));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL));
+		SUBBLOCK_OFFSET(REG_SQ_PROGRAM_CNTL));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL));
+		SUBBLOCK_OFFSET(REG_RB_DEPTHCONTROL));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE));
+		SUBBLOCK_OFFSET(REG_PA_SU_POINT_SIZE));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL));
+		SUBBLOCK_OFFSET(REG_PA_SC_LINE_CNTL));
 	GSL_RB_WRITE(cmds, cmds_gpu,
-		GSL_HAL_SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
+		SUBBLOCK_OFFSET(REG_PA_SU_POLY_OFFSET_FRONT_SCALE));
 
 	/* Vertex and Pixel Shader Start Addresses in instructions
 	* (3 DWORDS per instruction) */