)]}'
{
  "commit": "0e5f61b00c577da698fb00cd9c91a96b79044dfd",
  "tree": "de9e4c79ff38247988859e41350212b41fe882df",
  "parents": [
    "260f659b232b17889e3f0c9bf411675898b222c2"
  ],
  "author": {
    "name": "Andi Kleen",
    "email": "ak@suse.de",
    "time": "Sat Jul 29 21:42:37 2006 +0200"
  },
  "committer": {
    "name": "Linus Torvalds",
    "email": "torvalds@g5.osdl.org",
    "time": "Sat Jul 29 20:59:55 2006 -0700"
  },
  "message": "[PATCH] x86_64: On Intel systems when CPU has C3 don\u0027t use TSC\n\nOn Intel systems generally the TSC stops in C3 or deeper,\nso don\u0027t use it there. Follows similar logic on i386.\n\nThis should fix problems on Meroms.\n\nSigned-off-by: Andi Kleen \u003cak@suse.de\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@osdl.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e0341c6808e5ecc91d1850edb21c1a0244dbcaed",
      "old_mode": 33188,
      "old_path": "arch/x86_64/kernel/time.c",
      "new_id": "7a9b18224182ced7cd0932b2691249c69f70e4ad",
      "new_mode": 33188,
      "new_path": "arch/x86_64/kernel/time.c"
    }
  ]
}