msm: clock-9615: Disable hw clock gating for certain clocks
The bootchain is configuring these clocks in hw gating
mode: usb_hs1_p_clk, usb_hsic_p_clk, ce1_core_clk
This causes the hardware to always leave these clocks on.
Disable hardware clock gating on these clocks and and
return control to software.
CRs-Fixed: 319354
Change-Id: I4526126167e5a8150a20dfd53670d6e23bbecae5
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c
index 5974300..78da29c 100644
--- a/arch/arm/mach-msm/clock-9615.c
+++ b/arch/arm/mach-msm/clock-9615.c
@@ -1877,6 +1877,19 @@
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regval = readl_relaxed(LCC_PRI_PLL_CLK_CTL_REG);
writel_relaxed(regval | BIT(0), LCC_PRI_PLL_CLK_CTL_REG);
+
+ /* Disable hardware clock gating on certain clocks */
+ regval = readl_relaxed(USB_HSIC_HCLK_CTL_REG);
+ regval &= ~BIT(6);
+ writel_relaxed(regval, USB_HSIC_HCLK_CTL_REG);
+
+ regval = readl_relaxed(CE1_CORE_CLK_CTL_REG);
+ regval &= ~BIT(6);
+ writel_relaxed(regval, CE1_CORE_CLK_CTL_REG);
+
+ regval = readl_relaxed(USB_HS1_HCLK_CTL_REG);
+ regval &= ~BIT(6);
+ writel_relaxed(regval, USB_HS1_HCLK_CTL_REG);
}
/* Local clock driver initialization. */