[ARM] Remove compatibility layer for ARM irqs
set_irq_chipdata -> set_irq_chip_data
get_irq_chipdata -> get_irq_chip_data
do_level_IRQ -> handle_level_irq
do_edge_IRQ -> handle_edge_irq
do_simple_IRQ -> handle_simple_irq
irqdesc -> irq_desc
irqchip -> irq_chip
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 23d5bee..379efe7 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -88,7 +88,7 @@
static void
bast_pc104_maskack(unsigned int irqno)
{
- struct irqdesc *desc = irq_desc + IRQ_ISA;
+ struct irq_desc *desc = irq_desc + IRQ_ISA;
bast_pc104_mask(irqno);
desc->chip->ack(IRQ_ISA);
@@ -104,7 +104,7 @@
__raw_writeb(temp, BAST_VA_PC104_IRQMASK);
}
-static struct irqchip bast_pc104_chip = {
+static struct irq_chip bast_pc104_chip = {
.mask = bast_pc104_mask,
.unmask = bast_pc104_unmask,
.ack = bast_pc104_maskack
@@ -112,7 +112,7 @@
static void
bast_irq_pc104_demux(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
unsigned int stat;
unsigned int irqno;
@@ -157,7 +157,7 @@
unsigned int irqno = bast_pc104_irqs[i];
set_irq_chip(irqno, &bast_pc104_chip);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 683b349..e7d2ad9 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -180,7 +180,7 @@
__raw_writel(mask, S3C2410_INTMSK);
}
-struct irqchip s3c_irq_level_chip = {
+struct irq_chip s3c_irq_level_chip = {
.name = "s3c-level",
.ack = s3c_irq_maskack,
.mask = s3c_irq_mask,
@@ -188,7 +188,7 @@
.set_wake = s3c_irq_wake
};
-static struct irqchip s3c_irq_chip = {
+static struct irq_chip s3c_irq_chip = {
.name = "s3c",
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
@@ -344,7 +344,7 @@
return 0;
}
-static struct irqchip s3c_irqext_chip = {
+static struct irq_chip s3c_irqext_chip = {
.name = "s3c-ext",
.mask = s3c_irqext_mask,
.unmask = s3c_irqext_unmask,
@@ -353,7 +353,7 @@
.set_wake = s3c_irqext_wake
};
-static struct irqchip s3c_irq_eint0t4 = {
+static struct irq_chip s3c_irq_eint0t4 = {
.name = "s3c-ext0",
.ack = s3c_irq_ack,
.mask = s3c_irq_mask,
@@ -390,7 +390,7 @@
s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
}
-static struct irqchip s3c_irq_uart0 = {
+static struct irq_chip s3c_irq_uart0 = {
.name = "s3c-uart0",
.mask = s3c_irq_uart0_mask,
.unmask = s3c_irq_uart0_unmask,
@@ -417,7 +417,7 @@
s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
}
-static struct irqchip s3c_irq_uart1 = {
+static struct irq_chip s3c_irq_uart1 = {
.name = "s3c-uart1",
.mask = s3c_irq_uart1_mask,
.unmask = s3c_irq_uart1_unmask,
@@ -444,7 +444,7 @@
s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
}
-static struct irqchip s3c_irq_uart2 = {
+static struct irq_chip s3c_irq_uart2 = {
.name = "s3c-uart2",
.mask = s3c_irq_uart2_mask,
.unmask = s3c_irq_uart2_unmask,
@@ -471,7 +471,7 @@
s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
}
-static struct irqchip s3c_irq_adc = {
+static struct irq_chip s3c_irq_adc = {
.name = "s3c-adc",
.mask = s3c_irq_adc_mask,
.unmask = s3c_irq_adc_unmask,
@@ -480,11 +480,11 @@
/* irq demux for adc */
static void s3c_irq_demux_adc(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
unsigned int subsrc, submsk;
unsigned int offset = 9;
- struct irqdesc *mydesc;
+ struct irq_desc *mydesc;
/* read the current pending interrupts, and the mask
* for what it is available */
@@ -512,7 +512,7 @@
{
unsigned int subsrc, submsk;
unsigned int offset = start - IRQ_S3CUART_RX0;
- struct irqdesc *desc;
+ struct irq_desc *desc;
/* read the current pending interrupts, and the mask
* for what it is available */
@@ -549,7 +549,7 @@
static void
s3c_irq_demux_uart0(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
irq = irq;
s3c_irq_demux_uart(IRQ_S3CUART_RX0);
@@ -557,7 +557,7 @@
static void
s3c_irq_demux_uart1(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
irq = irq;
s3c_irq_demux_uart(IRQ_S3CUART_RX1);
@@ -565,7 +565,7 @@
static void
s3c_irq_demux_uart2(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
irq = irq;
s3c_irq_demux_uart(IRQ_S3CUART_RX2);
@@ -573,7 +573,7 @@
static void
s3c_irq_demux_extint8(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -595,7 +595,7 @@
static void
s3c_irq_demux_extint4t7(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
@@ -738,7 +738,7 @@
case IRQ_UART2:
case IRQ_ADCPARENT:
set_irq_chip(irqno, &s3c_irq_level_chip);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
break;
case IRQ_RESERVED6:
@@ -749,7 +749,7 @@
default:
//irqdbf("registering irq %d (s3c irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_chip);
- set_irq_handler(irqno, do_edge_IRQ);
+ set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
}
@@ -769,14 +769,14 @@
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
irqdbf("registering irq %d (ext int)\n", irqno);
set_irq_chip(irqno, &s3c_irq_eint0t4);
- set_irq_handler(irqno, do_edge_IRQ);
+ set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
irqdbf("registering irq %d (extended s3c irq)\n", irqno);
set_irq_chip(irqno, &s3c_irqext_chip);
- set_irq_handler(irqno, do_edge_IRQ);
+ set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
@@ -787,28 +787,28 @@
for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_uart0);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_uart1);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_uart2);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
irqdbf("registering irq %d (s3c adc irq)\n", irqno);
set_irq_chip(irqno, &s3c_irq_adc);
- set_irq_handler(irqno, do_edge_IRQ);
+ set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
diff --git a/arch/arm/mach-s3c2410/irq.h b/arch/arm/mach-s3c2410/irq.h
index 842a9f4..3686a00 100644
--- a/arch/arm/mach-s3c2410/irq.h
+++ b/arch/arm/mach-s3c2410/irq.h
@@ -17,7 +17,7 @@
#define EXTINT_OFF (IRQ_EINT4 - 4)
-extern struct irqchip s3c_irq_level_chip;
+extern struct irq_chip s3c_irq_level_chip;
static inline void
s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
diff --git a/arch/arm/mach-s3c2410/s3c2412-irq.c b/arch/arm/mach-s3c2410/s3c2412-irq.c
index 7f74154..ffcc30b 100644
--- a/arch/arm/mach-s3c2410/s3c2412-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2412-irq.c
@@ -98,7 +98,7 @@
__raw_writel(mask & ~bitval, S3C2410_INTMSK);
}
-static struct irqchip s3c2412_irq_eint0t4 = {
+static struct irq_chip s3c2412_irq_eint0t4 = {
.ack = s3c2412_irq_ack,
.mask = s3c2412_irq_mask,
.unmask = s3c2412_irq_unmask,
@@ -112,7 +112,7 @@
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
set_irq_chip(irqno, &s3c2412_irq_eint0t4);
- set_irq_handler(irqno, do_edge_IRQ);
+ set_irq_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID);
}
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 39db075..1ba19b2 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -42,10 +42,10 @@
/* WDT/AC97 */
static void s3c_irq_demux_wdtac97(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
unsigned int subsrc, submsk;
- struct irqdesc *mydesc;
+ struct irq_desc *mydesc;
/* read the current pending interrupts, and the mask
* for what it is available */
@@ -90,7 +90,7 @@
s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13);
}
-static struct irqchip s3c_irq_wdtac97 = {
+static struct irq_chip s3c_irq_wdtac97 = {
.mask = s3c_irq_wdtac97_mask,
.unmask = s3c_irq_wdtac97_unmask,
.ack = s3c_irq_wdtac97_ack,
@@ -105,12 +105,12 @@
/* add new chained handler for wdt, ac7 */
set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
- set_irq_handler(IRQ_WDT, do_level_IRQ);
+ set_irq_handler(IRQ_WDT, handle_level_irq);
set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
set_irq_chip(irqno, &s3c_irq_wdtac97);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
index 146f210..ede9463 100644
--- a/arch/arm/mach-s3c2410/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -42,10 +42,10 @@
/* camera irq */
static void s3c_irq_demux_cam(unsigned int irq,
- struct irqdesc *desc)
+ struct irq_desc *desc)
{
unsigned int subsrc, submsk;
- struct irqdesc *mydesc;
+ struct irq_desc *mydesc;
/* read the current pending interrupts, and the mask
* for what it is available */
@@ -89,7 +89,7 @@
s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
}
-static struct irqchip s3c_irq_cam = {
+static struct irq_chip s3c_irq_cam = {
.mask = s3c_irq_cam_mask,
.unmask = s3c_irq_cam_unmask,
.ack = s3c_irq_cam_ack,
@@ -100,18 +100,18 @@
unsigned int irqno;
set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
- set_irq_handler(IRQ_NFCON, do_level_IRQ);
+ set_irq_handler(IRQ_NFCON, handle_level_irq);
set_irq_flags(IRQ_NFCON, IRQF_VALID);
/* add chained handler for camera */
set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
- set_irq_handler(IRQ_CAM, do_level_IRQ);
+ set_irq_handler(IRQ_CAM, handle_level_irq);
set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
set_irq_chip(irqno, &s3c_irq_cam);
- set_irq_handler(irqno, do_level_IRQ);
+ set_irq_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID);
}