msm: clock-copper: Remove block reset ability from most clocks
The block reset functionality requires certain constraints
that cannot be enforced by the clock driver, but must be
respected by individual drivers. Remove the capability to
do a block reset from most clocks, with the intention of
adding it back in for drivers that require it on a case
by case basis.
Add a warning to catch callers of clk_reset on clocks that
don't have the block reset capability explicitly added
back in.
Change-Id: Ia0dc869cc1d5edc6dcd5ee014111f4ce792edee2
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-copper.c b/arch/arm/mach-msm/clock-copper.c
index 4d5f773..fc0b0af 100644
--- a/arch/arm/mach-msm/clock-copper.c
+++ b/arch/arm/mach-msm/clock-copper.c
@@ -1398,7 +1398,6 @@
.cbcr_reg = BAM_DMA_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(12),
- .bcr_reg = BAM_DMA_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_bam_dma_ahb_clk",
@@ -1411,7 +1410,6 @@
.cbcr_reg = BLSP1_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(17),
- .bcr_reg = BLSP1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_ahb_clk",
@@ -1424,7 +1422,6 @@
.cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP1_QUP1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
@@ -1436,7 +1433,6 @@
static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
.parent = &blsp1_qup1_spi_apps_clk_src.c,
- .bcr_reg = BLSP1_QUP1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
@@ -1449,7 +1445,6 @@
.cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP1_QUP2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
@@ -1461,7 +1456,6 @@
static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
.parent = &blsp1_qup2_spi_apps_clk_src.c,
- .bcr_reg = BLSP1_QUP2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
@@ -1474,7 +1468,6 @@
.cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP1_QUP3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
@@ -1486,7 +1479,6 @@
static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
.parent = &blsp1_qup3_spi_apps_clk_src.c,
- .bcr_reg = BLSP1_QUP3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
@@ -1499,7 +1491,6 @@
.cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP1_QUP4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
@@ -1511,7 +1502,6 @@
static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
.parent = &blsp1_qup4_spi_apps_clk_src.c,
- .bcr_reg = BLSP1_QUP4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
@@ -1524,7 +1514,6 @@
.cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP1_QUP5_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup5_i2c_apps_clk",
@@ -1536,7 +1525,6 @@
static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR,
.parent = &blsp1_qup5_spi_apps_clk_src.c,
- .bcr_reg = BLSP1_QUP5_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup5_spi_apps_clk",
@@ -1549,7 +1537,6 @@
.cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP1_QUP6_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup6_i2c_apps_clk",
@@ -1561,7 +1548,6 @@
static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = {
.cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR,
.parent = &blsp1_qup6_spi_apps_clk_src.c,
- .bcr_reg = BLSP1_QUP6_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_qup6_spi_apps_clk",
@@ -1573,7 +1559,6 @@
static struct branch_clk gcc_blsp1_uart1_apps_clk = {
.cbcr_reg = BLSP1_UART1_APPS_CBCR,
.parent = &blsp1_uart1_apps_clk_src.c,
- .bcr_reg = BLSP1_UART1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_uart1_apps_clk",
@@ -1585,7 +1570,6 @@
static struct branch_clk gcc_blsp1_uart2_apps_clk = {
.cbcr_reg = BLSP1_UART2_APPS_CBCR,
.parent = &blsp1_uart2_apps_clk_src.c,
- .bcr_reg = BLSP1_UART2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_uart2_apps_clk",
@@ -1597,7 +1581,6 @@
static struct branch_clk gcc_blsp1_uart3_apps_clk = {
.cbcr_reg = BLSP1_UART3_APPS_CBCR,
.parent = &blsp1_uart3_apps_clk_src.c,
- .bcr_reg = BLSP1_UART3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_uart3_apps_clk",
@@ -1609,7 +1592,6 @@
static struct branch_clk gcc_blsp1_uart4_apps_clk = {
.cbcr_reg = BLSP1_UART4_APPS_CBCR,
.parent = &blsp1_uart4_apps_clk_src.c,
- .bcr_reg = BLSP1_UART4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_uart4_apps_clk",
@@ -1621,7 +1603,6 @@
static struct branch_clk gcc_blsp1_uart5_apps_clk = {
.cbcr_reg = BLSP1_UART5_APPS_CBCR,
.parent = &blsp1_uart5_apps_clk_src.c,
- .bcr_reg = BLSP1_UART5_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_uart5_apps_clk",
@@ -1633,7 +1614,6 @@
static struct branch_clk gcc_blsp1_uart6_apps_clk = {
.cbcr_reg = BLSP1_UART6_APPS_CBCR,
.parent = &blsp1_uart6_apps_clk_src.c,
- .bcr_reg = BLSP1_UART6_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp1_uart6_apps_clk",
@@ -1646,7 +1626,6 @@
.cbcr_reg = BOOT_ROM_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(10),
- .bcr_reg = BOOT_ROM_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_boot_rom_ahb_clk",
@@ -1659,7 +1638,6 @@
.cbcr_reg = BLSP2_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(15),
- .bcr_reg = BLSP2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_ahb_clk",
@@ -1672,7 +1650,6 @@
.cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP2_QUP1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
@@ -1684,7 +1661,6 @@
static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
.parent = &blsp2_qup1_spi_apps_clk_src.c,
- .bcr_reg = BLSP2_QUP1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
@@ -1697,7 +1673,6 @@
.cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP2_QUP2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
@@ -1709,7 +1684,6 @@
static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
.parent = &blsp2_qup2_spi_apps_clk_src.c,
- .bcr_reg = BLSP2_QUP2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
@@ -1722,7 +1696,6 @@
.cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP2_QUP3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
@@ -1734,7 +1707,6 @@
static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
.parent = &blsp2_qup3_spi_apps_clk_src.c,
- .bcr_reg = BLSP2_QUP3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
@@ -1747,7 +1719,6 @@
.cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP2_QUP4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
@@ -1759,7 +1730,6 @@
static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
.parent = &blsp2_qup4_spi_apps_clk_src.c,
- .bcr_reg = BLSP2_QUP4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
@@ -1772,7 +1742,6 @@
.cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP2_QUP5_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup5_i2c_apps_clk",
@@ -1784,7 +1753,6 @@
static struct branch_clk gcc_blsp2_qup5_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP5_SPI_APPS_CBCR,
.parent = &blsp2_qup5_spi_apps_clk_src.c,
- .bcr_reg = BLSP2_QUP5_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup5_spi_apps_clk",
@@ -1797,7 +1765,6 @@
.cbcr_reg = BLSP2_QUP6_I2C_APPS_CBCR,
.parent = &cxo_clk_src.c,
.has_sibling = 1,
- .bcr_reg = BLSP2_QUP6_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup6_i2c_apps_clk",
@@ -1809,7 +1776,6 @@
static struct branch_clk gcc_blsp2_qup6_spi_apps_clk = {
.cbcr_reg = BLSP2_QUP6_SPI_APPS_CBCR,
.parent = &blsp2_qup6_spi_apps_clk_src.c,
- .bcr_reg = BLSP2_QUP6_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_qup6_spi_apps_clk",
@@ -1821,7 +1787,6 @@
static struct branch_clk gcc_blsp2_uart1_apps_clk = {
.cbcr_reg = BLSP2_UART1_APPS_CBCR,
.parent = &blsp2_uart1_apps_clk_src.c,
- .bcr_reg = BLSP2_UART1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_uart1_apps_clk",
@@ -1833,7 +1798,6 @@
static struct branch_clk gcc_blsp2_uart2_apps_clk = {
.cbcr_reg = BLSP2_UART2_APPS_CBCR,
.parent = &blsp2_uart2_apps_clk_src.c,
- .bcr_reg = BLSP2_UART2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_uart2_apps_clk",
@@ -1845,7 +1809,6 @@
static struct branch_clk gcc_blsp2_uart3_apps_clk = {
.cbcr_reg = BLSP2_UART3_APPS_CBCR,
.parent = &blsp2_uart3_apps_clk_src.c,
- .bcr_reg = BLSP2_UART3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_uart3_apps_clk",
@@ -1857,7 +1820,6 @@
static struct branch_clk gcc_blsp2_uart4_apps_clk = {
.cbcr_reg = BLSP2_UART4_APPS_CBCR,
.parent = &blsp2_uart4_apps_clk_src.c,
- .bcr_reg = BLSP2_UART4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_uart4_apps_clk",
@@ -1869,7 +1831,6 @@
static struct branch_clk gcc_blsp2_uart5_apps_clk = {
.cbcr_reg = BLSP2_UART5_APPS_CBCR,
.parent = &blsp2_uart5_apps_clk_src.c,
- .bcr_reg = BLSP2_UART5_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_uart5_apps_clk",
@@ -1881,7 +1842,6 @@
static struct branch_clk gcc_blsp2_uart6_apps_clk = {
.cbcr_reg = BLSP2_UART6_APPS_CBCR,
.parent = &blsp2_uart6_apps_clk_src.c,
- .bcr_reg = BLSP2_UART6_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_blsp2_uart6_apps_clk",
@@ -1894,7 +1854,6 @@
.cbcr_reg = CE1_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(5),
- .bcr_reg = CE1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_ce1_clk",
@@ -1907,7 +1866,6 @@
.cbcr_reg = CE1_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(3),
- .bcr_reg = CE1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_ce1_ahb_clk",
@@ -1920,7 +1878,6 @@
.cbcr_reg = CE1_AXI_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(4),
- .bcr_reg = CE1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_ce1_axi_clk",
@@ -1933,7 +1890,6 @@
.cbcr_reg = CE2_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(2),
- .bcr_reg = CE2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_ce2_clk",
@@ -1946,7 +1902,6 @@
.cbcr_reg = CE2_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(0),
- .bcr_reg = CE2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_ce1_ahb_clk",
@@ -1959,7 +1914,6 @@
.cbcr_reg = CE2_AXI_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(1),
- .bcr_reg = CE2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_ce1_axi_clk",
@@ -2004,7 +1958,6 @@
static struct branch_clk gcc_pdm2_clk = {
.cbcr_reg = PDM2_CBCR,
.parent = &pdm2_clk_src.c,
- .bcr_reg = PDM_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_pdm2_clk",
@@ -2016,7 +1969,6 @@
static struct branch_clk gcc_pdm_ahb_clk = {
.cbcr_reg = PDM_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = PDM_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_pdm_ahb_clk",
@@ -2029,7 +1981,6 @@
.cbcr_reg = PRNG_AHB_CBCR,
.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
.en_mask = BIT(13),
- .bcr_reg = PRNG_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_prng_ahb_clk",
@@ -2041,7 +1992,6 @@
static struct branch_clk gcc_sdcc1_ahb_clk = {
.cbcr_reg = SDCC1_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = SDCC1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc1_ahb_clk",
@@ -2053,7 +2003,6 @@
static struct branch_clk gcc_sdcc1_apps_clk = {
.cbcr_reg = SDCC1_APPS_CBCR,
.parent = &sdcc1_apps_clk_src.c,
- .bcr_reg = SDCC1_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc1_apps_clk",
@@ -2065,7 +2014,6 @@
static struct branch_clk gcc_sdcc2_ahb_clk = {
.cbcr_reg = SDCC2_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = SDCC2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc2_ahb_clk",
@@ -2077,7 +2025,6 @@
static struct branch_clk gcc_sdcc2_apps_clk = {
.cbcr_reg = SDCC2_APPS_CBCR,
.parent = &sdcc2_apps_clk_src.c,
- .bcr_reg = SDCC2_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc2_apps_clk",
@@ -2089,7 +2036,6 @@
static struct branch_clk gcc_sdcc3_ahb_clk = {
.cbcr_reg = SDCC3_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = SDCC3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc3_ahb_clk",
@@ -2101,7 +2047,6 @@
static struct branch_clk gcc_sdcc3_apps_clk = {
.cbcr_reg = SDCC3_APPS_CBCR,
.parent = &sdcc3_apps_clk_src.c,
- .bcr_reg = SDCC3_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc3_apps_clk",
@@ -2113,7 +2058,6 @@
static struct branch_clk gcc_sdcc4_ahb_clk = {
.cbcr_reg = SDCC4_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = SDCC4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc4_ahb_clk",
@@ -2125,7 +2069,6 @@
static struct branch_clk gcc_sdcc4_apps_clk = {
.cbcr_reg = SDCC4_APPS_CBCR,
.parent = &sdcc4_apps_clk_src.c,
- .bcr_reg = SDCC4_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_sdcc4_apps_clk",
@@ -2137,7 +2080,6 @@
static struct branch_clk gcc_tsif_ahb_clk = {
.cbcr_reg = TSIF_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = TSIF_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_tsif_ahb_clk",
@@ -2149,7 +2091,6 @@
static struct branch_clk gcc_tsif_ref_clk = {
.cbcr_reg = TSIF_REF_CBCR,
.parent = &tsif_ref_clk_src.c,
- .bcr_reg = TSIF_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_tsif_ref_clk",
@@ -2162,7 +2103,6 @@
.cbcr_reg = USB30_MASTER_CBCR,
.parent = &usb30_master_clk_src.c,
.has_sibling = 1,
- .bcr_reg = USB_30_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb30_master_clk",
@@ -2174,7 +2114,6 @@
static struct branch_clk gcc_usb30_mock_utmi_clk = {
.cbcr_reg = USB30_MOCK_UTMI_CBCR,
.parent = &usb30_mock_utmi_clk_src.c,
- .bcr_reg = USB_30_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb30_mock_utmi_clk",
@@ -2186,7 +2125,6 @@
static struct branch_clk gcc_usb_hs_ahb_clk = {
.cbcr_reg = USB_HS_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = USB_HS_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb_hs_ahb_clk",
@@ -2198,7 +2136,6 @@
static struct branch_clk gcc_usb_hs_system_clk = {
.cbcr_reg = USB_HS_SYSTEM_CBCR,
.parent = &usb_hs_system_clk_src.c,
- .bcr_reg = USB_HS_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb_hs_system_clk",
@@ -2210,7 +2147,6 @@
static struct branch_clk gcc_usb_hsic_ahb_clk = {
.cbcr_reg = USB_HSIC_AHB_CBCR,
.has_sibling = 1,
- .bcr_reg = USB_HS_HSIC_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb_hsic_ahb_clk",
@@ -2222,7 +2158,6 @@
static struct branch_clk gcc_usb_hsic_clk = {
.cbcr_reg = USB_HSIC_CBCR,
.parent = &usb_hsic_clk_src.c,
- .bcr_reg = USB_HS_HSIC_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb_hsic_clk",
@@ -2234,7 +2169,6 @@
static struct branch_clk gcc_usb_hsic_io_cal_clk = {
.cbcr_reg = USB_HSIC_IO_CAL_CBCR,
.parent = &usb_hsic_io_cal_clk_src.c,
- .bcr_reg = USB_HS_HSIC_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb_hsic_io_cal_clk",
@@ -2246,7 +2180,6 @@
static struct branch_clk gcc_usb_hsic_system_clk = {
.cbcr_reg = USB_HSIC_SYSTEM_CBCR,
.parent = &usb_hsic_system_clk_src.c,
- .bcr_reg = USB_HS_HSIC_BCR,
.base = &virt_bases[GCC_BASE],
.c = {
.dbg_name = "gcc_usb_hsic_system_clk",
@@ -2938,7 +2871,6 @@
.cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CCI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_cci_cci_ahb_clk",
@@ -2951,7 +2883,6 @@
.cbcr_reg = CAMSS_CCI_CCI_CBCR,
.parent = &cci_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_CCI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_cci_cci_clk",
@@ -2964,7 +2895,6 @@
.cbcr_reg = CAMSS_CSI0_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi0_ahb_clk",
@@ -2977,7 +2907,6 @@
.cbcr_reg = CAMSS_CSI0_CBCR,
.parent = &csi0_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi0_clk",
@@ -2990,7 +2919,6 @@
.cbcr_reg = CAMSS_CSI0PHY_CBCR,
.parent = &csi0_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI0PHY_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi0phy_clk",
@@ -3003,7 +2931,6 @@
.cbcr_reg = CAMSS_CSI0PIX_CBCR,
.parent = &csi0_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI0PIX_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi0pix_clk",
@@ -3016,7 +2943,6 @@
.cbcr_reg = CAMSS_CSI0RDI_CBCR,
.parent = &csi0_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI0RDI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi0rdi_clk",
@@ -3029,7 +2955,6 @@
.cbcr_reg = CAMSS_CSI1_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI1_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi1_ahb_clk",
@@ -3042,7 +2967,6 @@
.cbcr_reg = CAMSS_CSI1_CBCR,
.parent = &csi1_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI1_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi1_clk",
@@ -3055,7 +2979,6 @@
.cbcr_reg = CAMSS_CSI1PHY_CBCR,
.parent = &csi1_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI1PHY_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi1phy_clk",
@@ -3068,7 +2991,6 @@
.cbcr_reg = CAMSS_CSI1PIX_CBCR,
.parent = &csi1_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI1PIX_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi1pix_clk",
@@ -3081,7 +3003,6 @@
.cbcr_reg = CAMSS_CSI1RDI_CBCR,
.parent = &csi1_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI1RDI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi1rdi_clk",
@@ -3094,7 +3015,6 @@
.cbcr_reg = CAMSS_CSI2_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI2_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi2_ahb_clk",
@@ -3107,7 +3027,6 @@
.cbcr_reg = CAMSS_CSI2_CBCR,
.parent = &csi2_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI2_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi2_clk",
@@ -3120,7 +3039,6 @@
.cbcr_reg = CAMSS_CSI2PHY_CBCR,
.parent = &csi2_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI2PHY_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi2phy_clk",
@@ -3133,7 +3051,6 @@
.cbcr_reg = CAMSS_CSI2PIX_CBCR,
.parent = &csi2_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI2PIX_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi2pix_clk",
@@ -3146,7 +3063,6 @@
.cbcr_reg = CAMSS_CSI2RDI_CBCR,
.parent = &csi2_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI2RDI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi2rdi_clk",
@@ -3159,7 +3075,6 @@
.cbcr_reg = CAMSS_CSI3_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI3_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi3_ahb_clk",
@@ -3172,7 +3087,6 @@
.cbcr_reg = CAMSS_CSI3_CBCR,
.parent = &csi3_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI3_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi3_clk",
@@ -3185,7 +3099,6 @@
.cbcr_reg = CAMSS_CSI3PHY_CBCR,
.parent = &csi3_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI3PHY_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi3phy_clk",
@@ -3198,7 +3111,6 @@
.cbcr_reg = CAMSS_CSI3PIX_CBCR,
.parent = &csi3_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI3PIX_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi3pix_clk",
@@ -3211,7 +3123,6 @@
.cbcr_reg = CAMSS_CSI3RDI_CBCR,
.parent = &csi3_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI3RDI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi3rdi_clk",
@@ -3224,7 +3135,6 @@
.cbcr_reg = CAMSS_CSI_VFE0_CBCR,
.parent = &vfe0_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI_VFE0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi_vfe0_clk",
@@ -3237,7 +3147,6 @@
.cbcr_reg = CAMSS_CSI_VFE1_CBCR,
.parent = &vfe1_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_CSI_VFE1_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_csi_vfe1_clk",
@@ -3250,7 +3159,6 @@
.cbcr_reg = CAMSS_GP0_CBCR,
.parent = &mmss_gp0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_GP0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_gp0_clk",
@@ -3263,7 +3171,6 @@
.cbcr_reg = CAMSS_GP1_CBCR,
.parent = &mmss_gp1_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_GP1_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_gp1_clk",
@@ -3276,7 +3183,6 @@
.cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_ISPIF_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_ispif_ahb_clk",
@@ -3289,7 +3195,6 @@
.cbcr_reg = CAMSS_JPEG_JPEG0_CBCR,
.parent = &jpeg0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_JPEG_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_jpeg_jpeg0_clk",
@@ -3302,7 +3207,6 @@
.cbcr_reg = CAMSS_JPEG_JPEG1_CBCR,
.parent = &jpeg1_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_JPEG_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_jpeg_jpeg1_clk",
@@ -3315,7 +3219,6 @@
.cbcr_reg = CAMSS_JPEG_JPEG2_CBCR,
.parent = &jpeg2_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_JPEG_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_jpeg_jpeg2_clk",
@@ -3328,7 +3231,6 @@
.cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_JPEG_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_jpeg_jpeg_ahb_clk",
@@ -3341,7 +3243,6 @@
.cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_JPEG_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_jpeg_jpeg_axi_clk",
@@ -3353,7 +3254,6 @@
static struct branch_clk camss_jpeg_jpeg_ocmemnoc_clk = {
.cbcr_reg = CAMSS_JPEG_JPEG_OCMEMNOC_CBCR,
.has_sibling = 1,
- .bcr_reg = CAMSS_JPEG_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_jpeg_jpeg_ocmemnoc_clk",
@@ -3366,7 +3266,6 @@
.cbcr_reg = CAMSS_MCLK0_CBCR,
.parent = &mclk0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_MCLK0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_mclk0_clk",
@@ -3379,7 +3278,6 @@
.cbcr_reg = CAMSS_MCLK1_CBCR,
.parent = &mclk1_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_MCLK1_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_mclk1_clk",
@@ -3392,7 +3290,6 @@
.cbcr_reg = CAMSS_MCLK2_CBCR,
.parent = &mclk2_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_MCLK2_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_mclk2_clk",
@@ -3405,7 +3302,6 @@
.cbcr_reg = CAMSS_MCLK3_CBCR,
.parent = &mclk3_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_MCLK3_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_mclk3_clk",
@@ -3418,7 +3314,6 @@
.cbcr_reg = CAMSS_MICRO_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_MICRO_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_micro_ahb_clk",
@@ -3431,7 +3326,6 @@
.cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR,
.parent = &csi0phytimer_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_PHY0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_phy0_csi0phytimer_clk",
@@ -3444,7 +3338,6 @@
.cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR,
.parent = &csi1phytimer_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_PHY1_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_phy1_csi1phytimer_clk",
@@ -3457,7 +3350,6 @@
.cbcr_reg = CAMSS_PHY2_CSI2PHYTIMER_CBCR,
.parent = &csi2phytimer_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_PHY2_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_phy2_csi2phytimer_clk",
@@ -3470,7 +3362,6 @@
.cbcr_reg = CAMSS_TOP_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_TOP_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_top_ahb_clk",
@@ -3483,7 +3374,6 @@
.cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_cpp_ahb_clk",
@@ -3496,7 +3386,6 @@
.cbcr_reg = CAMSS_VFE_CPP_CBCR,
.parent = &cpp_clk_src.c,
.has_sibling = 0,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_cpp_clk",
@@ -3509,7 +3398,6 @@
.cbcr_reg = CAMSS_VFE_VFE0_CBCR,
.parent = &vfe0_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_vfe0_clk",
@@ -3522,7 +3410,6 @@
.cbcr_reg = CAMSS_VFE_VFE1_CBCR,
.parent = &vfe1_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_vfe1_clk",
@@ -3535,7 +3422,6 @@
.cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_vfe_ahb_clk",
@@ -3548,7 +3434,6 @@
.cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_vfe_axi_clk",
@@ -3560,7 +3445,6 @@
static struct branch_clk camss_vfe_vfe_ocmemnoc_clk = {
.cbcr_reg = CAMSS_VFE_VFE_OCMEMNOC_CBCR,
.has_sibling = 1,
- .bcr_reg = CAMSS_VFE_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "camss_vfe_vfe_ocmemnoc_clk",
@@ -3573,7 +3457,6 @@
.cbcr_reg = MDSS_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_ahb_clk",
@@ -3586,7 +3469,6 @@
.cbcr_reg = MDSS_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_axi_clk",
@@ -3599,7 +3481,6 @@
.cbcr_reg = MDSS_BYTE0_CBCR,
.parent = &byte0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_byte0_clk",
@@ -3612,7 +3493,6 @@
.cbcr_reg = MDSS_BYTE1_CBCR,
.parent = &byte1_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_byte1_clk",
@@ -3625,7 +3505,6 @@
.cbcr_reg = MDSS_EDPAUX_CBCR,
.parent = &edpaux_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_edpaux_clk",
@@ -3638,7 +3517,6 @@
.cbcr_reg = MDSS_EDPLINK_CBCR,
.parent = &edplink_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_edplink_clk",
@@ -3651,7 +3529,6 @@
.cbcr_reg = MDSS_EDPPIXEL_CBCR,
.parent = &edppixel_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_edppixel_clk",
@@ -3664,7 +3541,6 @@
.cbcr_reg = MDSS_ESC0_CBCR,
.parent = &esc0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_esc0_clk",
@@ -3677,7 +3553,6 @@
.cbcr_reg = MDSS_ESC1_CBCR,
.parent = &esc1_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_esc1_clk",
@@ -3690,7 +3565,6 @@
.cbcr_reg = MDSS_EXTPCLK_CBCR,
.parent = &extpclk_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_extpclk_clk",
@@ -3703,7 +3577,6 @@
.cbcr_reg = MDSS_HDMI_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_hdmi_ahb_clk",
@@ -3716,7 +3589,6 @@
.cbcr_reg = MDSS_HDMI_CBCR,
.parent = &hdmi_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_hdmi_clk",
@@ -3729,7 +3601,6 @@
.cbcr_reg = MDSS_MDP_CBCR,
.parent = &mdp_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_mdp_clk",
@@ -3742,7 +3613,6 @@
.cbcr_reg = MDSS_MDP_LUT_CBCR,
.parent = &mdp_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_mdp_lut_clk",
@@ -3755,7 +3625,6 @@
.cbcr_reg = MDSS_PCLK0_CBCR,
.parent = &pclk0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_pclk0_clk",
@@ -3768,7 +3637,6 @@
.cbcr_reg = MDSS_PCLK1_CBCR,
.parent = &pclk1_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_pclk1_clk",
@@ -3781,7 +3649,6 @@
.cbcr_reg = MDSS_VSYNC_CBCR,
.parent = &vsync_clk_src.c,
.has_sibling = 0,
- .bcr_reg = MDSS_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mdss_vsync_clk",
@@ -3794,7 +3661,6 @@
.cbcr_reg = MMSS_MISC_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MMSSNOCAHB_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mmss_misc_ahb_clk",
@@ -3807,7 +3673,6 @@
.cbcr_reg = MMSS_MMSSNOC_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MMSSNOCAHB_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mmss_mmssnoc_ahb_clk",
@@ -3820,7 +3685,6 @@
.cbcr_reg = MMSS_MMSSNOC_BTO_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MMSSNOCAHB_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mmss_mmssnoc_bto_ahb_clk",
@@ -3833,7 +3697,6 @@
.cbcr_reg = MMSS_MMSSNOC_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MMSSNOCAXI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mmss_mmssnoc_axi_clk",
@@ -3846,7 +3709,6 @@
.cbcr_reg = MMSS_S0_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = MMSSNOCAXI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "mmss_s0_axi_clk",
@@ -3859,7 +3721,6 @@
.cbcr_reg = VENUS0_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = VENUS0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "venus0_ahb_clk",
@@ -3872,7 +3733,6 @@
.cbcr_reg = VENUS0_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = VENUS0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "venus0_axi_clk",
@@ -3884,7 +3744,6 @@
static struct branch_clk venus0_ocmemnoc_clk = {
.cbcr_reg = VENUS0_OCMEMNOC_CBCR,
.has_sibling = 1,
- .bcr_reg = VENUS0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "venus0_ocmemnoc_clk",
@@ -3897,7 +3756,6 @@
.cbcr_reg = VENUS0_VCODEC0_CBCR,
.parent = &vcodec0_clk_src.c,
.has_sibling = 0,
- .bcr_reg = VENUS0_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "venus0_vcodec0_clk",
@@ -3909,7 +3767,6 @@
static struct branch_clk oxili_gfx3d_clk = {
.cbcr_reg = OXILI_GFX3D_CBCR,
.has_sibling = 1,
- .bcr_reg = OXILI_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "oxili_gfx3d_clk",
@@ -3922,7 +3779,6 @@
.cbcr_reg = OXILICX_AHB_CBCR,
.parent = &ahb_clk_src.c,
.has_sibling = 1,
- .bcr_reg = OXILICX_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "oxilicx_ahb_clk",
@@ -3935,7 +3791,6 @@
.cbcr_reg = OXILICX_AXI_CBCR,
.parent = &axi_clk_src.c,
.has_sibling = 1,
- .bcr_reg = OXILICX_BCR,
.base = &virt_bases[MMSS_BASE],
.c = {
.dbg_name = "oxilicx_axi_clk",
@@ -4370,7 +4225,6 @@
static struct branch_clk mss_bus_q6_clk = {
.cbcr_reg = MSS_BUS_Q6_CBCR,
- .bcr_reg = MSS_Q6SS_BCR,
.has_sibling = 1,
.base = &virt_bases[MSS_BASE],
.c = {
diff --git a/arch/arm/mach-msm/clock-local2.c b/arch/arm/mach-msm/clock-local2.c
index 355a6d3..cf45e63 100644
--- a/arch/arm/mach-msm/clock-local2.c
+++ b/arch/arm/mach-msm/clock-local2.c
@@ -462,14 +462,16 @@
}
static int __branch_clk_reset(void __iomem *bcr_reg,
- enum clk_reset_action action)
+ enum clk_reset_action action, const char *name)
{
int ret = 0;
unsigned long flags;
u32 reg_val;
- if (!bcr_reg)
+ if (!bcr_reg) {
+ WARN("clk_reset called on an unsupported clock (%s)\n", name);
return -EPERM;
+ }
spin_lock_irqsave(&local_clock_reg_lock, flags);
reg_val = readl_relaxed(bcr_reg);
@@ -495,7 +497,7 @@
static int branch_clk_reset(struct clk *c, enum clk_reset_action action)
{
struct branch_clk *branch = to_branch_clk(c);
- return __branch_clk_reset(BCR_REG(branch), action);
+ return __branch_clk_reset(BCR_REG(branch), action, c->dbg_name);
}
/*
@@ -504,7 +506,7 @@
static int local_vote_clk_reset(struct clk *c, enum clk_reset_action action)
{
struct local_vote_clk *vclk = to_local_vote_clk(c);
- return __branch_clk_reset(BCR_REG(vclk), action);
+ return __branch_clk_reset(BCR_REG(vclk), action, c->dbg_name);
}
static int local_vote_clk_enable(struct clk *c)