msm: pil-q6v5: Update QDSP6SS RESET and PWR_CTL registers
Hardware documentation has been corrected, changing the bit
positions and reset states for this register. Update software
accordingly.
Change-Id: I35ef0e38e9fb64574c74d1082a11af760340f982
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/pil-q6v5.c b/arch/arm/mach-msm/pil-q6v5.c
index b27d5e5..d6ad2aa3 100644
--- a/arch/arm/mach-msm/pil-q6v5.c
+++ b/arch/arm/mach-msm/pil-q6v5.c
@@ -40,15 +40,15 @@
#define HALT_ACK_TIMEOUT_US 100000
/* QDSP6SS_RESET */
+#define Q6SS_STOP_CORE BIT(0)
#define Q6SS_CORE_ARES BIT(1)
-#define Q6SS_ETM_ISDB_ARES BIT(3)
-#define Q6SS_STOP_CORE BIT(4)
+#define Q6SS_BUS_ARES_ENA BIT(2)
/* QDSP6SS_GFMUX_CTL */
#define Q6SS_CLK_ENA BIT(1)
/* QDSP6SS_PWR_CTL */
-#define Q6SS_L2DATA_SLP_NRET_N BIT(0)
+#define Q6SS_L2DATA_SLP_NRET_N (BIT(0)|BIT(1)|BIT(2))
#define Q6SS_L2TAG_SLP_NRET_N BIT(16)
#define Q6SS_ETB_SLP_NRET_N BIT(17)
#define Q6SS_L2DATA_STBY_N BIT(18)
@@ -179,7 +179,7 @@
/* Assert Q6 resets */
val = readl_relaxed(drv->reg_base + QDSP6SS_RESET);
- val = (Q6SS_CORE_ARES | Q6SS_ETM_ISDB_ARES);
+ val = (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENA);
writel_relaxed(val, drv->reg_base + QDSP6SS_RESET);
/* Kill power at block headswitch (affects LPASS only) */
@@ -196,7 +196,7 @@
/* Assert resets, stop core */
val = readl_relaxed(drv->reg_base + QDSP6SS_RESET);
- val |= (Q6SS_CORE_ARES | Q6SS_ETM_ISDB_ARES | Q6SS_STOP_CORE);
+ val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENA | Q6SS_STOP_CORE);
writel_relaxed(val, drv->reg_base + QDSP6SS_RESET);
/* Enable power block headswitch (only affects LPASS) */
@@ -216,7 +216,8 @@
writel_relaxed(val, drv->reg_base + QDSP6SS_PWR_CTL);
/* Bring core out of reset */
- val = Q6SS_STOP_CORE;
+ val = readl_relaxed(drv->reg_base + QDSP6SS_RESET);
+ val &= ~Q6SS_CORE_ARES;
writel_relaxed(val, drv->reg_base + QDSP6SS_RESET);
/* Disable clock gating for core and rclk */