sh: Fixup cpu_data references for the non-boot CPUs.
There are a lot of bogus cpu_data-> references that only end up working
for the boot CPU, convert these to current_cpu_data to fixup SMP.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 6c3c768..4b339a6 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -48,7 +48,7 @@
{
unsigned long ccr, flags;
- if (cpu_data->type == CPU_SH_NONE)
+ if (current_cpu_data.type == CPU_SH_NONE)
panic("Unknown CPU");
jump_to_P2();
@@ -68,7 +68,7 @@
if (ccr & CCR_CACHE_ENABLE) {
unsigned long ways, waysize, addrstart;
- waysize = cpu_data->dcache.sets;
+ waysize = current_cpu_data.dcache.sets;
#ifdef CCR_CACHE_ORA
/*
@@ -79,7 +79,7 @@
waysize >>= 1;
#endif
- waysize <<= cpu_data->dcache.entry_shift;
+ waysize <<= current_cpu_data.dcache.entry_shift;
#ifdef CCR_CACHE_EMODE
/* If EMODE is not set, we only have 1 way to flush. */
@@ -87,7 +87,7 @@
ways = 1;
else
#endif
- ways = cpu_data->dcache.ways;
+ ways = current_cpu_data.dcache.ways;
addrstart = CACHE_OC_ADDRESS_ARRAY;
do {
@@ -95,10 +95,10 @@
for (addr = addrstart;
addr < addrstart + waysize;
- addr += cpu_data->dcache.linesz)
+ addr += current_cpu_data.dcache.linesz)
ctrl_outl(0, addr);
- addrstart += cpu_data->dcache.way_incr;
+ addrstart += current_cpu_data.dcache.way_incr;
} while (--ways);
}
@@ -110,7 +110,7 @@
#ifdef CCR_CACHE_EMODE
/* Force EMODE if possible */
- if (cpu_data->dcache.ways > 1)
+ if (current_cpu_data.dcache.ways > 1)
flags |= CCR_CACHE_EMODE;
else
flags &= ~CCR_CACHE_EMODE;
@@ -127,10 +127,10 @@
#ifdef CONFIG_SH_OCRAM
/* Turn on OCRAM -- halve the OC */
flags |= CCR_CACHE_ORA;
- cpu_data->dcache.sets >>= 1;
+ current_cpu_data.dcache.sets >>= 1;
- cpu_data->dcache.way_size = cpu_data->dcache.sets *
- cpu_data->dcache.linesz;
+ current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
+ current_cpu_data.dcache.linesz;
#endif
ctrl_outl(flags, CCR);
@@ -172,7 +172,7 @@
/* If the DSP bit is still set, this CPU has a DSP */
if (sr & SR_DSP)
- cpu_data->flags |= CPU_HAS_DSP;
+ current_cpu_data.flags |= CPU_HAS_DSP;
/* Now that we've determined the DSP status, clear the DSP bit. */
release_dsp();
@@ -204,18 +204,18 @@
cache_init();
shm_align_mask = max_t(unsigned long,
- cpu_data->dcache.way_size - 1,
+ current_cpu_data.dcache.way_size - 1,
PAGE_SIZE - 1);
/* Disable the FPU */
if (fpu_disabled) {
printk("FPU Disabled\n");
- cpu_data->flags &= ~CPU_HAS_FPU;
+ current_cpu_data.flags &= ~CPU_HAS_FPU;
disable_fpu();
}
/* FPU initialization */
- if ((cpu_data->flags & CPU_HAS_FPU)) {
+ if ((current_cpu_data.flags & CPU_HAS_FPU)) {
clear_thread_flag(TIF_USEDFPU);
clear_used_math();
}
@@ -233,7 +233,7 @@
/* Disable the DSP */
if (dsp_disabled) {
printk("DSP Disabled\n");
- cpu_data->flags &= ~CPU_HAS_DSP;
+ current_cpu_data.flags &= ~CPU_HAS_DSP;
release_dsp();
}
#endif
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index ba527d9..108e81b 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -18,27 +18,27 @@
int __init detect_cpu_and_cache_system(void)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7604)
- cpu_data->type = CPU_SH7604;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1<<10);
- cpu_data->dcache.sets = 64;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.type = CPU_SH7604;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1<<10);
+ current_cpu_data.dcache.sets = 64;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
- cpu_data->type = CPU_SH7619;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1<<12);
- cpu_data->dcache.sets = 256;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.type = CPU_SH7619;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1<<12);
+ current_cpu_data.dcache.sets = 256;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
#endif
/*
* SH-2 doesn't have separate caches
*/
- cpu_data->dcache.flags |= SH_CACHE_COMBINED;
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 87c6c05..426f6db 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -17,14 +17,14 @@
int __init detect_cpu_and_cache_system(void)
{
/* Just SH7206 for now .. */
- cpu_data->type = CPU_SH7206;
+ current_cpu_data.type = CPU_SH7206;
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.way_incr = (1 << 11);
- cpu_data->dcache.sets = 128;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.way_incr = (1 << 11);
+ current_cpu_data.dcache.sets = 128;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
/*
* The icache is the same as the dcache as far as this setup is
@@ -32,7 +32,7 @@
* lacks the U bit that the dcache has, none of this has any bearing
* on the cache info.
*/
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index e670988..821b0ab 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -50,41 +50,41 @@
back_to_P1();
- cpu_data->dcache.ways = 4;
- cpu_data->dcache.entry_shift = 4;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
- cpu_data->dcache.flags = 0;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.dcache.entry_shift = 4;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.flags = 0;
/*
* 7709A/7729 has 16K cache (256-entry), while 7702 has only
* 2K(direct) 7702 is not supported (yet)
*/
if (data0 == data1 && data2 == data3) { /* Shadow */
- cpu_data->dcache.way_incr = (1 << 11);
- cpu_data->dcache.entry_mask = 0x7f0;
- cpu_data->dcache.sets = 128;
- cpu_data->type = CPU_SH7708;
+ current_cpu_data.dcache.way_incr = (1 << 11);
+ current_cpu_data.dcache.entry_mask = 0x7f0;
+ current_cpu_data.dcache.sets = 128;
+ current_cpu_data.type = CPU_SH7708;
- cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC;
+ current_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
} else { /* 7709A or 7729 */
- cpu_data->dcache.way_incr = (1 << 12);
- cpu_data->dcache.entry_mask = 0xff0;
- cpu_data->dcache.sets = 256;
- cpu_data->type = CPU_SH7729;
+ current_cpu_data.dcache.way_incr = (1 << 12);
+ current_cpu_data.dcache.entry_mask = 0xff0;
+ current_cpu_data.dcache.sets = 256;
+ current_cpu_data.type = CPU_SH7729;
#if defined(CONFIG_CPU_SUBTYPE_SH7706)
- cpu_data->type = CPU_SH7706;
+ current_cpu_data.type = CPU_SH7706;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
- cpu_data->type = CPU_SH7710;
+ current_cpu_data.type = CPU_SH7710;
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
- cpu_data->type = CPU_SH7705;
+ current_cpu_data.type = CPU_SH7705;
#if defined(CONFIG_SH7705_CACHE_32KB)
- cpu_data->dcache.way_incr = (1 << 13);
- cpu_data->dcache.entry_mask = 0x1ff0;
- cpu_data->dcache.sets = 512;
+ current_cpu_data.dcache.way_incr = (1 << 13);
+ current_cpu_data.dcache.entry_mask = 0x1ff0;
+ current_cpu_data.dcache.sets = 512;
ctrl_outl(CCR_CACHE_32KB, CCR3);
#else
ctrl_outl(CCR_CACHE_16KB, CCR3);
@@ -95,8 +95,8 @@
/*
* SH-3 doesn't have separate caches
*/
- cpu_data->dcache.flags |= SH_CACHE_COMBINED;
- cpu_data->icache = cpu_data->dcache;
+ current_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
+ current_cpu_data.icache = current_cpu_data.dcache;
return 0;
}
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index b26e2bc..9d28c88 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -10,11 +10,10 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-
#include <linux/init.h>
+#include <linux/io.h>
#include <asm/processor.h>
#include <asm/cache.h>
-#include <asm/io.h>
int __init detect_cpu_and_cache_system(void)
{
@@ -36,20 +35,20 @@
/*
* Setup some sane SH-4 defaults for the icache
*/
- cpu_data->icache.way_incr = (1 << 13);
- cpu_data->icache.entry_shift = 5;
- cpu_data->icache.sets = 256;
- cpu_data->icache.ways = 1;
- cpu_data->icache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.icache.way_incr = (1 << 13);
+ current_cpu_data.icache.entry_shift = 5;
+ current_cpu_data.icache.sets = 256;
+ current_cpu_data.icache.ways = 1;
+ current_cpu_data.icache.linesz = L1_CACHE_BYTES;
/*
* And again for the dcache ..
*/
- cpu_data->dcache.way_incr = (1 << 14);
- cpu_data->dcache.entry_shift = 5;
- cpu_data->dcache.sets = 512;
- cpu_data->dcache.ways = 1;
- cpu_data->dcache.linesz = L1_CACHE_BYTES;
+ current_cpu_data.dcache.way_incr = (1 << 14);
+ current_cpu_data.dcache.entry_shift = 5;
+ current_cpu_data.dcache.sets = 512;
+ current_cpu_data.dcache.ways = 1;
+ current_cpu_data.dcache.linesz = L1_CACHE_BYTES;
/*
* Setup some generic flags we can probe
@@ -57,16 +56,16 @@
*/
if (((pvr >> 16) & 0xff) == 0x10) {
if ((cvr & 0x02000000) == 0)
- cpu_data->flags |= CPU_HAS_L2_CACHE;
+ current_cpu_data.flags |= CPU_HAS_L2_CACHE;
if ((cvr & 0x10000000) == 0)
- cpu_data->flags |= CPU_HAS_DSP;
+ current_cpu_data.flags |= CPU_HAS_DSP;
- cpu_data->flags |= CPU_HAS_LLSC;
+ current_cpu_data.flags |= CPU_HAS_LLSC;
}
/* FPU detection works for everyone */
if ((cvr & 0x20000000) == 1)
- cpu_data->flags |= CPU_HAS_FPU;
+ current_cpu_data.flags |= CPU_HAS_FPU;
/* Mask off the upper chip ID */
pvr &= 0xffff;
@@ -77,147 +76,151 @@
*/
switch (pvr) {
case 0x205:
- cpu_data->type = CPU_SH7750;
- cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
+ current_cpu_data.type = CPU_SH7750;
+ current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
CPU_HAS_PERF_COUNTER;
break;
case 0x206:
- cpu_data->type = CPU_SH7750S;
- cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
+ current_cpu_data.type = CPU_SH7750S;
+ current_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
CPU_HAS_PERF_COUNTER;
break;
case 0x1100:
- cpu_data->type = CPU_SH7751;
- cpu_data->flags |= CPU_HAS_FPU;
+ current_cpu_data.type = CPU_SH7751;
+ current_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x2000:
- cpu_data->type = CPU_SH73180;
- cpu_data->icache.ways = 4;
- cpu_data->dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_LLSC;
+ current_cpu_data.type = CPU_SH73180;
+ current_cpu_data.icache.ways = 4;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.flags |= CPU_HAS_LLSC;
break;
case 0x2001:
case 0x2004:
- cpu_data->type = CPU_SH7770;
- cpu_data->icache.ways = 4;
- cpu_data->dcache.ways = 4;
+ current_cpu_data.type = CPU_SH7770;
+ current_cpu_data.icache.ways = 4;
+ current_cpu_data.dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
+ current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
break;
case 0x2006:
case 0x200A:
if (prr == 0x61)
- cpu_data->type = CPU_SH7781;
+ current_cpu_data.type = CPU_SH7781;
else
- cpu_data->type = CPU_SH7780;
+ current_cpu_data.type = CPU_SH7780;
- cpu_data->icache.ways = 4;
- cpu_data->dcache.ways = 4;
+ current_cpu_data.icache.ways = 4;
+ current_cpu_data.dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+ current_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
CPU_HAS_LLSC;
break;
case 0x3000:
case 0x3003:
case 0x3009:
- cpu_data->type = CPU_SH7343;
- cpu_data->icache.ways = 4;
- cpu_data->dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_LLSC;
+ current_cpu_data.type = CPU_SH7343;
+ current_cpu_data.icache.ways = 4;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.flags |= CPU_HAS_LLSC;
break;
case 0x3008:
if (prr == 0xa0) {
- cpu_data->type = CPU_SH7722;
- cpu_data->icache.ways = 4;
- cpu_data->dcache.ways = 4;
- cpu_data->flags |= CPU_HAS_LLSC;
+ current_cpu_data.type = CPU_SH7722;
+ current_cpu_data.icache.ways = 4;
+ current_cpu_data.dcache.ways = 4;
+ current_cpu_data.flags |= CPU_HAS_LLSC;
}
break;
case 0x8000:
- cpu_data->type = CPU_ST40RA;
- cpu_data->flags |= CPU_HAS_FPU;
+ current_cpu_data.type = CPU_ST40RA;
+ current_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x8100:
- cpu_data->type = CPU_ST40GX1;
- cpu_data->flags |= CPU_HAS_FPU;
+ current_cpu_data.type = CPU_ST40GX1;
+ current_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x700:
- cpu_data->type = CPU_SH4_501;
- cpu_data->icache.ways = 2;
- cpu_data->dcache.ways = 2;
+ current_cpu_data.type = CPU_SH4_501;
+ current_cpu_data.icache.ways = 2;
+ current_cpu_data.dcache.ways = 2;
break;
case 0x600:
- cpu_data->type = CPU_SH4_202;
- cpu_data->icache.ways = 2;
- cpu_data->dcache.ways = 2;
- cpu_data->flags |= CPU_HAS_FPU;
+ current_cpu_data.type = CPU_SH4_202;
+ current_cpu_data.icache.ways = 2;
+ current_cpu_data.dcache.ways = 2;
+ current_cpu_data.flags |= CPU_HAS_FPU;
break;
case 0x500 ... 0x501:
switch (prr) {
case 0x10:
- cpu_data->type = CPU_SH7750R;
+ current_cpu_data.type = CPU_SH7750R;
break;
case 0x11:
- cpu_data->type = CPU_SH7751R;
+ current_cpu_data.type = CPU_SH7751R;
break;
case 0x50 ... 0x5f:
- cpu_data->type = CPU_SH7760;
+ current_cpu_data.type = CPU_SH7760;
break;
}
- cpu_data->icache.ways = 2;
- cpu_data->dcache.ways = 2;
+ current_cpu_data.icache.ways = 2;
+ current_cpu_data.dcache.ways = 2;
- cpu_data->flags |= CPU_HAS_FPU;
+ current_cpu_data.flags |= CPU_HAS_FPU;
break;
default:
- cpu_data->type = CPU_SH_NONE;
+ current_cpu_data.type = CPU_SH_NONE;
break;
}
#ifdef CONFIG_SH_DIRECT_MAPPED
- cpu_data->icache.ways = 1;
- cpu_data->dcache.ways = 1;
+ current_cpu_data.icache.ways = 1;
+ current_cpu_data.dcache.ways = 1;
+#endif
+
+#ifdef CONFIG_CPU_HAS_PTEA
+ current_cpu_data.flags |= CPU_HAS_PTEA;
#endif
/*
* On anything that's not a direct-mapped cache, look to the CVR
* for I/D-cache specifics.
*/
- if (cpu_data->icache.ways > 1) {
+ if (current_cpu_data.icache.ways > 1) {
size = sizes[(cvr >> 20) & 0xf];
- cpu_data->icache.way_incr = (size >> 1);
- cpu_data->icache.sets = (size >> 6);
+ current_cpu_data.icache.way_incr = (size >> 1);
+ current_cpu_data.icache.sets = (size >> 6);
}
/* Setup the rest of the I-cache info */
- cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
- cpu_data->icache.linesz;
+ current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
+ current_cpu_data.icache.linesz;
- cpu_data->icache.way_size = cpu_data->icache.sets *
- cpu_data->icache.linesz;
+ current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
+ current_cpu_data.icache.linesz;
/* And the rest of the D-cache */
- if (cpu_data->dcache.ways > 1) {
+ if (current_cpu_data.dcache.ways > 1) {
size = sizes[(cvr >> 16) & 0xf];
- cpu_data->dcache.way_incr = (size >> 1);
- cpu_data->dcache.sets = (size >> 6);
+ current_cpu_data.dcache.way_incr = (size >> 1);
+ current_cpu_data.dcache.sets = (size >> 6);
}
- cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
- cpu_data->dcache.linesz;
+ current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
+ current_cpu_data.dcache.linesz;
- cpu_data->dcache.way_size = cpu_data->dcache.sets *
- cpu_data->dcache.linesz;
+ current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
+ current_cpu_data.dcache.linesz;
/*
* Setup the L2 cache desc
*
* SH-4A's have an optional PIPT L2.
*/
- if (cpu_data->flags & CPU_HAS_L2_CACHE) {
+ if (current_cpu_data.flags & CPU_HAS_L2_CACHE) {
/*
* Size calculation is much more sensible
* than it is for the L1.
@@ -228,16 +231,22 @@
BUG_ON(!size);
- cpu_data->scache.way_incr = (1 << 16);
- cpu_data->scache.entry_shift = 5;
- cpu_data->scache.ways = 4;
- cpu_data->scache.linesz = L1_CACHE_BYTES;
- cpu_data->scache.entry_mask =
- (cpu_data->scache.way_incr - cpu_data->scache.linesz);
- cpu_data->scache.sets = size /
- (cpu_data->scache.linesz * cpu_data->scache.ways);
- cpu_data->scache.way_size =
- (cpu_data->scache.sets * cpu_data->scache.linesz);
+ current_cpu_data.scache.way_incr = (1 << 16);
+ current_cpu_data.scache.entry_shift = 5;
+ current_cpu_data.scache.ways = 4;
+ current_cpu_data.scache.linesz = L1_CACHE_BYTES;
+
+ current_cpu_data.scache.entry_mask =
+ (current_cpu_data.scache.way_incr -
+ current_cpu_data.scache.linesz);
+
+ current_cpu_data.scache.sets = size /
+ (current_cpu_data.scache.linesz *
+ current_cpu_data.scache.ways);
+
+ current_cpu_data.scache.way_size =
+ (current_cpu_data.scache.sets *
+ current_cpu_data.scache.linesz);
}
return 0;
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
index 0298f0f..9d6a438 100644
--- a/arch/sh/kernel/process.c
+++ b/arch/sh/kernel/process.c
@@ -293,13 +293,14 @@
#ifdef CONFIG_MMU
/* We don't have any ASID settings for the SH-2! */
- if (cpu_data->type != CPU_SH7604)
+ if (current_cpu_data.type != CPU_SH7604)
ctrl_outb(asid, UBC_BASRA);
#endif
ctrl_outl(0, UBC_BAMRA);
- if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) {
+ if (current_cpu_data.type == CPU_SH7729 ||
+ current_cpu_data.type == CPU_SH7710) {
ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
} else {
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index d6b817a..98802ab 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -1,14 +1,11 @@
/*
- * linux/arch/sh/kernel/setup.c
+ * arch/sh/kernel/setup.c
+ *
+ * This file handles the architecture-dependent parts of initialization
*
* Copyright (C) 1999 Niibe Yutaka
- * Copyright (C) 2002, 2003 Paul Mundt
+ * Copyright (C) 2002 - 2006 Paul Mundt
*/
-
-/*
- * This file handles the architecture-dependent parts of initialization
- */
-
#include <linux/screen_info.h>
#include <linux/ioport.h>
#include <linux/init.h>
@@ -395,9 +392,9 @@
[CPU_SH_NONE] = "Unknown"
};
-const char *get_cpu_subtype(void)
+const char *get_cpu_subtype(struct sh_cpuinfo *c)
{
- return cpu_name[boot_cpu_data.type];
+ return cpu_name[c->type];
}
#ifdef CONFIG_PROC_FS
@@ -407,19 +404,19 @@
"ptea", "llsc", "l2", NULL
};
-static void show_cpuflags(struct seq_file *m)
+static void show_cpuflags(struct seq_file *m, struct sh_cpuinfo *c)
{
unsigned long i;
seq_printf(m, "cpu flags\t:");
- if (!cpu_data->flags) {
+ if (!c->flags) {
seq_printf(m, " %s\n", cpu_flags[0]);
return;
}
for (i = 0; cpu_flags[i]; i++)
- if ((cpu_data->flags & (1 << i)))
+ if ((c->flags & (1 << i)))
seq_printf(m, " %s", cpu_flags[i+1]);
seq_printf(m, "\n");
@@ -441,16 +438,20 @@
*/
static int show_cpuinfo(struct seq_file *m, void *v)
{
- unsigned int cpu = smp_processor_id();
+ struct sh_cpuinfo *c = v;
+ unsigned int cpu = c - cpu_data;
- if (!cpu && cpu_online(cpu))
+ if (!cpu_online(cpu))
+ return 0;
+
+ if (cpu == 0)
seq_printf(m, "machine\t\t: %s\n", get_system_type());
seq_printf(m, "processor\t: %d\n", cpu);
seq_printf(m, "cpu family\t: %s\n", init_utsname()->machine);
- seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype());
+ seq_printf(m, "cpu type\t: %s\n", get_cpu_subtype(c));
- show_cpuflags(m);
+ show_cpuflags(m, c);
seq_printf(m, "cache type\t: ");
@@ -459,22 +460,22 @@
* unified cache on the SH-2 and SH-3, as well as the harvard
* style cache on the SH-4.
*/
- if (boot_cpu_data.icache.flags & SH_CACHE_COMBINED) {
+ if (c->icache.flags & SH_CACHE_COMBINED) {
seq_printf(m, "unified\n");
- show_cacheinfo(m, "cache", boot_cpu_data.icache);
+ show_cacheinfo(m, "cache", c->icache);
} else {
seq_printf(m, "split (harvard)\n");
- show_cacheinfo(m, "icache", boot_cpu_data.icache);
- show_cacheinfo(m, "dcache", boot_cpu_data.dcache);
+ show_cacheinfo(m, "icache", c->icache);
+ show_cacheinfo(m, "dcache", c->dcache);
}
/* Optional secondary cache */
- if (boot_cpu_data.flags & CPU_HAS_L2_CACHE)
- show_cacheinfo(m, "scache", boot_cpu_data.scache);
+ if (c->flags & CPU_HAS_L2_CACHE)
+ show_cacheinfo(m, "scache", c->scache);
seq_printf(m, "bogomips\t: %lu.%02lu\n",
- boot_cpu_data.loops_per_jiffy/(500000/HZ),
- (boot_cpu_data.loops_per_jiffy/(5000/HZ)) % 100);
+ c->loops_per_jiffy/(500000/HZ),
+ (c->loops_per_jiffy/(5000/HZ)) % 100);
return show_clocks(m);
}
diff --git a/arch/sh/kernel/signal.c b/arch/sh/kernel/signal.c
index 379c88b..32f10a0 100644
--- a/arch/sh/kernel/signal.c
+++ b/arch/sh/kernel/signal.c
@@ -127,7 +127,7 @@
{
struct task_struct *tsk = current;
- if (!(cpu_data->flags & CPU_HAS_FPU))
+ if (!(current_cpu_data.flags & CPU_HAS_FPU))
return 0;
set_used_math();
@@ -140,7 +140,7 @@
{
struct task_struct *tsk = current;
- if (!(cpu_data->flags & CPU_HAS_FPU))
+ if (!(current_cpu_data.flags & CPU_HAS_FPU))
return 0;
if (!used_math()) {
@@ -181,7 +181,7 @@
#undef COPY
#ifdef CONFIG_SH_FPU
- if (cpu_data->flags & CPU_HAS_FPU) {
+ if (current_cpu_data.flags & CPU_HAS_FPU) {
int owned_fp;
struct task_struct *tsk = current;
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index e91224f..e9f168f 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -641,7 +641,7 @@
* Safe guard if DSP mode is already enabled or we're lacking
* the DSP altogether.
*/
- if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
+ if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
return 0;
get_user(inst, ((unsigned short *) regs->pc));