)]}'
{
  "commit": "11d1578f9454159c43499d1d8fe8a7d728c176a3",
  "tree": "2ad986dad1482083c1f61632f851883791d70aea",
  "parents": [
    "9590b7ba3fefdfe0c7741f5e2f61faf2ffcea19c"
  ],
  "author": {
    "name": "Vince Weaver",
    "email": "vince@deater.net",
    "time": "Wed Jul 08 17:46:14 2009 -0400"
  },
  "committer": {
    "name": "Ingo Molnar",
    "email": "mingo@elte.hu",
    "time": "Fri Jul 10 10:28:26 2009 +0200"
  },
  "message": "perf_counter: Add P6 PMU support\n\nAdd basic P6 PMU support. The P6 uses the EVNTSEL0 EN bit to\nenable/disable both its counters. We use this for the\nglobal enable/disable, and clear all config bits (except EN)\nto disable individual counters.\n\nActual ia32 hardware doesn\u0027t support lfence, so use a locked\nop without side-effect to implement a full barrier.\n\nperf stat and perf record seem to function correctly.\n\n[a.p.zijlstra@chello.nl: cleanups and complete the enable/disable code]\n\nSigned-off-by: Vince Weaver \u003cvince@deater.net\u003e\nSigned-off-by: Peter Zijlstra \u003ca.p.zijlstra@chello.nl\u003e\nLKML-Reference: \u003cPine.LNX.4.64.0907081718450.2715@pianoman.cluster.toy\u003e\nSigned-off-by: Ingo Molnar \u003cmingo@elte.hu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "36c3dc7b8991d4a5b7ea8709c9003b161c058d6f",
      "old_mode": 33188,
      "old_path": "arch/x86/kernel/cpu/perf_counter.c",
      "new_id": "1910f39ff19a4d69e38b6ab1762d06bd2108fcb1",
      "new_mode": 33188,
      "new_path": "arch/x86/kernel/cpu/perf_counter.c"
    },
    {
      "type": "modify",
      "old_id": "27887c916439f24d83a4ba50fca53945142594d8",
      "old_mode": 33188,
      "old_path": "tools/perf/perf.h",
      "new_id": "53bb9550def9b3a76f543d62d00910d05cbaa14d",
      "new_mode": 33188,
      "new_path": "tools/perf/perf.h"
    }
  ]
}