Merge branch 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel-stable' of master.kernel.org:/home/rmk/linux-2.6-arm: (161 commits)
ARM: pxa: fix building issue of missing physmap.h
ARM: mmp: PXA910 drive strength FAST using wrong value
ARM: mmp: MMP2 drive strength FAST using wrong value
ARM: pxa: fix recursive calls in pxa_low_gpio_chip
AT91: Support for gsia18s board
AT91: Acme Systems FOX Board G20 board files
AT91: board-sam9m10g45ek.c: Remove duplicate inclusion of mach/hardware.h
ARM: pxa: fix suspend/resume array index miscalculation
ARM: pxa: use cpu_has_ipr() consistently in irq.c
ARM: pxa: remove unused variable in clock-pxa3xx.c
ARM: pxa: fix warning in zeus.c
ARM: sa1111: fix typo in sa1111_retrigger_lowirq()
ARM mxs: clkdev related compile fixes
ARM i.MX mx31_3ds: Fix MC13783 regulator names
ARM: plat-stmp3xxx: irq_data conversion.
ARM: plat-spear: irq_data conversion.
ARM: plat-orion: irq_data conversion.
ARM: plat-omap: irq_data conversion.
ARM: plat-nomadik: irq_data conversion.
ARM: plat-mxc: irq_data conversion.
...
Fix up trivial conflict in arch/arm/plat-omap/gpio.c (Lennert
Buytenhek's irq_data conversion clashing with some omap irq updates)
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index ccf2660..971d186 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -729,17 +729,17 @@
return -EINVAL;
}
-static int gpio_irq_type(unsigned irq, unsigned type)
+static int gpio_irq_type(struct irq_data *d, unsigned type)
{
struct gpio_bank *bank;
unsigned gpio;
int retval;
unsigned long flags;
- if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
- gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
+ if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
+ gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
else
- gpio = irq - IH_GPIO_BASE;
+ gpio = d->irq - IH_GPIO_BASE;
if (check_gpio(gpio) < 0)
return -EINVAL;
@@ -752,21 +752,21 @@
&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
- bank = get_irq_chip_data(irq);
+ bank = irq_data_get_irq_chip_data(d);
spin_lock_irqsave(&bank->lock, flags);
retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
if (retval == 0) {
- struct irq_desc *d = irq_to_desc(irq);
+ struct irq_desc *desc = irq_to_desc(d->irq);
- d->status &= ~IRQ_TYPE_SENSE_MASK;
- d->status |= type;
+ desc->status &= ~IRQ_TYPE_SENSE_MASK;
+ desc->status |= type;
}
spin_unlock_irqrestore(&bank->lock, flags);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
- __set_irq_handler_unlocked(irq, handle_level_irq);
+ __set_irq_handler_unlocked(d->irq, handle_level_irq);
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
- __set_irq_handler_unlocked(irq, handle_edge_irq);
+ __set_irq_handler_unlocked(d->irq, handle_edge_irq);
return retval;
}
@@ -1023,15 +1023,15 @@
}
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
-static int gpio_wake_enable(unsigned int irq, unsigned int enable)
+static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
+ unsigned int gpio = d->irq - IH_GPIO_BASE;
struct gpio_bank *bank;
int retval;
if (check_gpio(gpio) < 0)
return -ENODEV;
- bank = get_irq_chip_data(irq);
+ bank = irq_data_get_irq_chip_data(d);
retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
return retval;
@@ -1144,7 +1144,7 @@
u32 retrigger = 0;
int unmasked = 0;
- desc->chip->ack(irq);
+ desc->irq_data.chip->irq_ack(&desc->irq_data);
bank = get_irq_data(irq);
#ifdef CONFIG_ARCH_OMAP1
@@ -1201,7 +1201,7 @@
configured, we could unmask GPIO bank interrupt immediately */
if (!level_mask && !unmasked) {
unmasked = 1;
- desc->chip->unmask(irq);
+ desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
isr |= retrigger;
@@ -1237,41 +1237,40 @@
interrupt */
exit:
if (!unmasked)
- desc->chip->unmask(irq);
-
+ desc->irq_data.chip->irq_unmask(&desc->irq_data);
}
-static void gpio_irq_shutdown(unsigned int irq)
+static void gpio_irq_shutdown(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d->irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_reset_gpio(bank, gpio);
}
-static void gpio_ack_irq(unsigned int irq)
+static void gpio_ack_irq(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d->irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_clear_gpio_irqstatus(bank, gpio);
}
-static void gpio_mask_irq(unsigned int irq)
+static void gpio_mask_irq(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d->irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_set_gpio_irqenable(bank, gpio, 0);
_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
}
-static void gpio_unmask_irq(unsigned int irq)
+static void gpio_unmask_irq(struct irq_data *d)
{
- unsigned int gpio = irq - IH_GPIO_BASE;
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = d->irq - IH_GPIO_BASE;
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
unsigned int irq_mask = 1 << get_gpio_index(gpio);
- struct irq_desc *desc = irq_to_desc(irq);
+ struct irq_desc *desc = irq_to_desc(d->irq);
u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
if (trigger)
@@ -1289,12 +1288,12 @@
static struct irq_chip gpio_irq_chip = {
.name = "GPIO",
- .shutdown = gpio_irq_shutdown,
- .ack = gpio_ack_irq,
- .mask = gpio_mask_irq,
- .unmask = gpio_unmask_irq,
- .set_type = gpio_irq_type,
- .set_wake = gpio_wake_enable,
+ .irq_shutdown = gpio_irq_shutdown,
+ .irq_ack = gpio_ack_irq,
+ .irq_mask = gpio_mask_irq,
+ .irq_unmask = gpio_unmask_irq,
+ .irq_set_type = gpio_irq_type,
+ .irq_set_wake = gpio_wake_enable,
};
/*---------------------------------------------------------------------*/
@@ -1303,36 +1302,36 @@
/* MPUIO uses the always-on 32k clock */
-static void mpuio_ack_irq(unsigned int irq)
+static void mpuio_ack_irq(struct irq_data *d)
{
/* The ISR is reset automatically, so do nothing here. */
}
-static void mpuio_mask_irq(unsigned int irq)
+static void mpuio_mask_irq(struct irq_data *d)
{
- unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_set_gpio_irqenable(bank, gpio, 0);
}
-static void mpuio_unmask_irq(unsigned int irq)
+static void mpuio_unmask_irq(struct irq_data *d)
{
- unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
- struct gpio_bank *bank = get_irq_chip_data(irq);
+ unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
+ struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
_set_gpio_irqenable(bank, gpio, 1);
}
static struct irq_chip mpuio_irq_chip = {
.name = "MPUIO",
- .ack = mpuio_ack_irq,
- .mask = mpuio_mask_irq,
- .unmask = mpuio_unmask_irq,
- .set_type = gpio_irq_type,
+ .irq_ack = mpuio_ack_irq,
+ .irq_mask = mpuio_mask_irq,
+ .irq_unmask = mpuio_unmask_irq,
+ .irq_set_type = gpio_irq_type,
#ifdef CONFIG_ARCH_OMAP16XX
/* REVISIT: assuming only 16xx supports MPUIO wake events */
- .set_wake = gpio_wake_enable,
+ .irq_set_wake = gpio_wake_enable,
#endif
};