msm: qdss: CP14 based save and restore of debug and trace registers
Accessing Krait debug registers from memory mapped interface requires
qdss_pclkdbg_clk and qdss_h_clk clocks apart from the ETM clock. This
means either:
1. requesting or releasing qdss clocks for every save and restore
or
2. leaving the qdss clocks on all the time
or
3. using the CP14 interface which is based on just the ETM clock and
doesn't require the qdss clocks
We choose to use CP14 interface to avoid the pitfalls for 1. and 2. above.
Moreover, we make the save-restore autodetect the debug and trace
architecture and do the needful based on it and hence consolidate the
code for 8660 and 8960.
Change-Id: If2a383e6f755c9ed893031966fa7ef6de41a5699
Signed-off-by: Pratik Patel <pratikp@codeaurora.org>
diff --git a/arch/arm/configs/fsm9xxx-perf_defconfig b/arch/arm/configs/fsm9xxx-perf_defconfig
index 92d401c..3d4b37d 100644
--- a/arch/arm/configs/fsm9xxx-perf_defconfig
+++ b/arch/arm/configs/fsm9xxx-perf_defconfig
@@ -34,7 +34,7 @@
# CONFIG_MSM_HW3D is not set
# CONFIG_QSD_AUDIO is not set
# CONFIG_SURF_FFA_GPIO_KEYPAD is not set
-CONFIG_MSM_JTAG_V7=y
+CONFIG_MSM_JTAG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_VMSPLIT_2G=y
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index c793e1d..4209dc9 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -138,7 +138,6 @@
select MSM_AUDIO_QDSP6 if SND_SOC
select CPU_HAS_L2_PMU
select MSM_SPM_V2
- select HAS_QDSS
select MSM_L2_SPM
select MSM_NATIVE_RESTART
select DONT_MAP_HOLE_AFTER_MEMBANK0
@@ -1814,41 +1813,21 @@
make the kernel reboot on a kernel panic - that must be
enabled via another mechanism.
-config HAS_QDSS
- bool "QDSS Present"
+config MSM_JTAG
+ bool "JTAG debug and trace support"
help
- Select this if the chip has Qualcomm Debug Subsystem implemented.
-
-config MSM_DEBUG_ACROSS_PC
- bool "Debug support across power collapse"
- help
- Enables debug state to be saved and restored across power collapse.
-
-config MSM_JTAG_V7
- depends on CPU_V7 && !HAS_QDSS
- default y if DEBUG_KERNEL
- bool "JTAG debug support"
- select MSM_DEBUG_ACROSS_PC
- help
- Add additional support for JTAG kernel debugging.
-
-config MSM_TRACE_ACROSS_PC
- bool "Trace support across power collapse"
- help
- Enables trace state to be saved and restored across power collapse.
+ Add additional support for JTAG kernel debugging and tracing.
config MSM_ETM
tristate "Enable MSM ETM and ETB"
- depends on ARCH_MSM8X60 && !HAS_QDSS
- select MSM_TRACE_ACROSS_PC
+ depends on ARCH_MSM8X60
+ select MSM_JTAG
help
- Enables embedded trace collection on Qualcomm v7 CPUs.
+ Enables embedded trace collection on MSM8660
config MSM_QDSS
bool "Qualcomm Debug Subsystem"
- depends on HAS_QDSS
- select MSM_DEBUG_ACROSS_PC
- select MSM_TRACE_ACROSS_PC
+ select MSM_JTAG
help
Enables support for Qualcomm Debug Subsystem.
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 95f2535..dac36bb 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -45,17 +45,11 @@
obj-$(CONFIG_MSM_AVS_HW) += avs_hw.o
obj-$(CONFIG_CPU_V6) += idle-v6.o
obj-$(CONFIG_CPU_V7) += idle-v7.o
-obj-$(CONFIG_MSM_JTAG_V7) += jtag-v7.o
+obj-$(CONFIG_MSM_JTAG) += jtag.o
-msm-etm-objs := cp14.o etm.o
+msm-etm-objs := etm.o
obj-$(CONFIG_MSM_ETM) += msm-etm.o
-
-ifdef CONFIG_MSM_QDSS
- obj-y += qdss-debug.o
- obj-y += qdss-etb.o qdss-tpiu.o
- obj-y += qdss-funnel.o
- obj-y += qdss-ptm.o
-endif
+obj-$(CONFIG_MSM_QDSS) += qdss-etb.o qdss-tpiu.o qdss-funnel.o qdss-ptm.o
quiet_cmd_mkrpcsym = MKCAP $@
cmd_mkrpcsym = $(PERL) $(srctree)/$(src)/mkrpcsym.pl $< $@
diff --git a/arch/arm/mach-msm/board-8930.c b/arch/arm/mach-msm/board-8930.c
index 53f8621..fb4cc52 100644
--- a/arch/arm/mach-msm/board-8930.c
+++ b/arch/arm/mach-msm/board-8930.c
@@ -1593,7 +1593,6 @@
&msm_etb_device,
&msm_tpiu_device,
&msm_funnel_device,
- &msm_debug_device,
&msm_ptm_device,
#endif
&msm_device_dspcrashd_8960,
diff --git a/arch/arm/mach-msm/board-8960.c b/arch/arm/mach-msm/board-8960.c
index 15a3829..02659b2 100644
--- a/arch/arm/mach-msm/board-8960.c
+++ b/arch/arm/mach-msm/board-8960.c
@@ -1657,7 +1657,6 @@
&msm_etb_device,
&msm_tpiu_device,
&msm_funnel_device,
- &msm_debug_device,
&msm_ptm_device,
#endif
&msm_device_dspcrashd_8960,
diff --git a/arch/arm/mach-msm/cp14.S b/arch/arm/mach-msm/cp14.S
deleted file mode 100644
index 94c74d3..0000000
--- a/arch/arm/mach-msm/cp14.S
+++ /dev/null
@@ -1,669 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/threads.h>
-
-#if (NR_CPUS > 2)
-#error code only tested for 1 or 2 CPUs.
-#endif
-
-/* Add 1 slot to store the register count for ETM state */
-#define MAX_ETM_REGS (56 + 1)
-#define MAX_ETM_STATE_SIZE (MAX_ETM_REGS * 4)
-
-.global etm_read_reg
-etm_read_reg:
- cmp r0, #0x7F
- bhi read_high
- ldr r2, =read_table
- add r2, r2, r0, lsl #3
- mov pc, r2
-
-read_high:
- cmp r0, #0xC1
- beq read_c1
- cmp r0, #0xC4
- beq read_c4
- cmp r0, #0xC5
- beq read_c5
- mov r0, #0
- bx lr
-
-read_c1:
- mrc p14, 1, r0, c1, c1, 4 // register 0xC1 (OS Lock Status Reg)
- bx lr
-
-read_c4:
- mrc p14, 1, r0, c1, c4, 4 // register 0xC4 (Powerdown Ctl Reg)
- bx lr
-
-read_c5:
- mrc p14, 1, r0, c1, c5, 4 // register 0xC5 (Powerdown Status Reg)
- bx lr
-
-read_table:
- mrc p14, 1, r0, c0, c0, 0 // register 0x00
- bx lr
- mrc p14, 1, r0, c0, c1, 0 // register 0x01
- bx lr
- mrc p14, 1, r0, c0, c2, 0 // register 0x02
- bx lr
- mrc p14, 1, r0, c0, c3, 0 // register 0x03
- bx lr
- mrc p14, 1, r0, c0, c4, 0 // register 0x04
- bx lr
- mrc p14, 1, r0, c0, c5, 0 // register 0x05
- bx lr
- mrc p14, 1, r0, c0, c6, 0 // register 0x06
- bx lr
- mrc p14, 1, r0, c0, c7, 0 // register 0x07
- bx lr
- mrc p14, 1, r0, c0, c8, 0 // register 0x08
- bx lr
- mrc p14, 1, r0, c0, c9, 0 // register 0x09
- bx lr
- mrc p14, 1, r0, c0, c10, 0 // register 0x0A
- bx lr
- mrc p14, 1, r0, c0, c11, 0 // register 0x0B
- bx lr
- mrc p14, 1, r0, c0, c12, 0 // register 0x0C
- bx lr
- mrc p14, 1, r0, c0, c13, 0 // register 0x0D
- bx lr
- mrc p14, 1, r0, c0, c14, 0 // register 0x0E
- bx lr
- mrc p14, 1, r0, c0, c15, 0 // register 0x0F
- bx lr
- mrc p14, 1, r0, c0, c0, 1 // register 0x10
- bx lr
- mrc p14, 1, r0, c0, c1, 1 // register 0x11
- bx lr
- mrc p14, 1, r0, c0, c2, 1 // register 0x12
- bx lr
- mrc p14, 1, r0, c0, c3, 1 // register 0x13
- bx lr
- mrc p14, 1, r0, c0, c4, 1 // register 0x14
- bx lr
- mrc p14, 1, r0, c0, c5, 1 // register 0x15
- bx lr
- mrc p14, 1, r0, c0, c6, 1 // register 0x16
- bx lr
- mrc p14, 1, r0, c0, c7, 1 // register 0x17
- bx lr
- mrc p14, 1, r0, c0, c8, 1 // register 0x18
- bx lr
- mrc p14, 1, r0, c0, c9, 1 // register 0x19
- bx lr
- mrc p14, 1, r0, c0, c10, 1 // register 0x1A
- bx lr
- mrc p14, 1, r0, c0, c11, 1 // register 0x1B
- bx lr
- mrc p14, 1, r0, c0, c12, 1 // register 0x1C
- bx lr
- mrc p14, 1, r0, c0, c13, 1 // register 0x1D
- bx lr
- mrc p14, 1, r0, c0, c14, 1 // register 0x1E
- bx lr
- mrc p14, 1, r0, c0, c15, 1 // register 0x1F
- bx lr
- mrc p14, 1, r0, c0, c0, 2 // register 0x20
- bx lr
- mrc p14, 1, r0, c0, c1, 2 // register 0x21
- bx lr
- mrc p14, 1, r0, c0, c2, 2 // register 0x22
- bx lr
- mrc p14, 1, r0, c0, c3, 2 // register 0x23
- bx lr
- mrc p14, 1, r0, c0, c4, 2 // register 0x24
- bx lr
- mrc p14, 1, r0, c0, c5, 2 // register 0x25
- bx lr
- mrc p14, 1, r0, c0, c6, 2 // register 0x26
- bx lr
- mrc p14, 1, r0, c0, c7, 2 // register 0x27
- bx lr
- mrc p14, 1, r0, c0, c8, 2 // register 0x28
- bx lr
- mrc p14, 1, r0, c0, c9, 2 // register 0x29
- bx lr
- mrc p14, 1, r0, c0, c10, 2 // register 0x2A
- bx lr
- mrc p14, 1, r0, c0, c11, 2 // register 0x2B
- bx lr
- mrc p14, 1, r0, c0, c12, 2 // register 0x2C
- bx lr
- mrc p14, 1, r0, c0, c13, 2 // register 0x2D
- bx lr
- mrc p14, 1, r0, c0, c14, 2 // register 0x2E
- bx lr
- mrc p14, 1, r0, c0, c15, 2 // register 0x2F
- bx lr
- mrc p14, 1, r0, c0, c0, 3 // register 0x30
- bx lr
- mrc p14, 1, r0, c0, c1, 3 // register 0x31
- bx lr
- mrc p14, 1, r0, c0, c2, 3 // register 0x32
- bx lr
- mrc p14, 1, r0, c0, c3, 3 // register 0x33
- bx lr
- mrc p14, 1, r0, c0, c4, 3 // register 0x34
- bx lr
- mrc p14, 1, r0, c0, c5, 3 // register 0x35
- bx lr
- mrc p14, 1, r0, c0, c6, 3 // register 0x36
- bx lr
- mrc p14, 1, r0, c0, c7, 3 // register 0x37
- bx lr
- mrc p14, 1, r0, c0, c8, 3 // register 0x38
- bx lr
- mrc p14, 1, r0, c0, c9, 3 // register 0x39
- bx lr
- mrc p14, 1, r0, c0, c10, 3 // register 0x3A
- bx lr
- mrc p14, 1, r0, c0, c11, 3 // register 0x3B
- bx lr
- mrc p14, 1, r0, c0, c12, 3 // register 0x3C
- bx lr
- mrc p14, 1, r0, c0, c13, 3 // register 0x3D
- bx lr
- mrc p14, 1, r0, c0, c14, 3 // register 0x3E
- bx lr
- mrc p14, 1, r0, c0, c15, 3 // register 0x3F
- bx lr
- mrc p14, 1, r0, c0, c0, 4 // register 0x40
- bx lr
- mrc p14, 1, r0, c0, c1, 4 // register 0x41
- bx lr
- mrc p14, 1, r0, c0, c2, 4 // register 0x42
- bx lr
- mrc p14, 1, r0, c0, c3, 4 // register 0x43
- bx lr
- mrc p14, 1, r0, c0, c4, 4 // register 0x44
- bx lr
- mrc p14, 1, r0, c0, c5, 4 // register 0x45
- bx lr
- mrc p14, 1, r0, c0, c6, 4 // register 0x46
- bx lr
- mrc p14, 1, r0, c0, c7, 4 // register 0x47
- bx lr
- mrc p14, 1, r0, c0, c8, 4 // register 0x48
- bx lr
- mrc p14, 1, r0, c0, c9, 4 // register 0x49
- bx lr
- mrc p14, 1, r0, c0, c10, 4 // register 0x4A
- bx lr
- mrc p14, 1, r0, c0, c11, 4 // register 0x4B
- bx lr
- mrc p14, 1, r0, c0, c12, 4 // register 0x4C
- bx lr
- mrc p14, 1, r0, c0, c13, 4 // register 0x4D
- bx lr
- mrc p14, 1, r0, c0, c14, 4 // register 0x4E
- bx lr
- mrc p14, 1, r0, c0, c15, 4 // register 0x4F
- bx lr
- mrc p14, 1, r0, c0, c0, 5 // register 0x50
- bx lr
- mrc p14, 1, r0, c0, c1, 5 // register 0x51
- bx lr
- mrc p14, 1, r0, c0, c2, 5 // register 0x52
- bx lr
- mrc p14, 1, r0, c0, c3, 5 // register 0x53
- bx lr
- mrc p14, 1, r0, c0, c4, 5 // register 0x54
- bx lr
- mrc p14, 1, r0, c0, c5, 5 // register 0x55
- bx lr
- mrc p14, 1, r0, c0, c6, 5 // register 0x56
- bx lr
- mrc p14, 1, r0, c0, c7, 5 // register 0x57
- bx lr
- mrc p14, 1, r0, c0, c8, 5 // register 0x58
- bx lr
- mrc p14, 1, r0, c0, c9, 5 // register 0x59
- bx lr
- mrc p14, 1, r0, c0, c10, 5 // register 0x5A
- bx lr
- mrc p14, 1, r0, c0, c11, 5 // register 0x5B
- bx lr
- mrc p14, 1, r0, c0, c12, 5 // register 0x5C
- bx lr
- mrc p14, 1, r0, c0, c13, 5 // register 0x5D
- bx lr
- mrc p14, 1, r0, c0, c14, 5 // register 0x5E
- bx lr
- mrc p14, 1, r0, c0, c15, 5 // register 0x5F
- bx lr
- mrc p14, 1, r0, c0, c0, 6 // register 0x60
- bx lr
- mrc p14, 1, r0, c0, c1, 6 // register 0x61
- bx lr
- mrc p14, 1, r0, c0, c2, 6 // register 0x62
- bx lr
- mrc p14, 1, r0, c0, c3, 6 // register 0x63
- bx lr
- mrc p14, 1, r0, c0, c4, 6 // register 0x64
- bx lr
- mrc p14, 1, r0, c0, c5, 6 // register 0x65
- bx lr
- mrc p14, 1, r0, c0, c6, 6 // register 0x66
- bx lr
- mrc p14, 1, r0, c0, c7, 6 // register 0x67
- bx lr
- mrc p14, 1, r0, c0, c8, 6 // register 0x68
- bx lr
- mrc p14, 1, r0, c0, c9, 6 // register 0x69
- bx lr
- mrc p14, 1, r0, c0, c10, 6 // register 0x6A
- bx lr
- mrc p14, 1, r0, c0, c11, 6 // register 0x6B
- bx lr
- mrc p14, 1, r0, c0, c12, 6 // register 0x6C
- bx lr
- mrc p14, 1, r0, c0, c13, 6 // register 0x6D
- bx lr
- mrc p14, 1, r0, c0, c14, 6 // register 0x6E
- bx lr
- mrc p14, 1, r0, c0, c15, 6 // register 0x6F
- bx lr
- mrc p14, 1, r0, c0, c0, 7 // register 0x70
- bx lr
- mrc p14, 1, r0, c0, c1, 7 // register 0x71
- bx lr
- mrc p14, 1, r0, c0, c2, 7 // register 0x72
- bx lr
- mrc p14, 1, r0, c0, c3, 7 // register 0x73
- bx lr
- mrc p14, 1, r0, c0, c4, 7 // register 0x74
- bx lr
- mrc p14, 1, r0, c0, c5, 7 // register 0x75
- bx lr
- mrc p14, 1, r0, c0, c6, 7 // register 0x76
- bx lr
- mrc p14, 1, r0, c0, c7, 7 // register 0x77
- bx lr
- mrc p14, 1, r0, c0, c8, 7 // register 0x78
- bx lr
- mrc p14, 1, r0, c0, c9, 7 // register 0x79
- bx lr
- mrc p14, 1, r0, c0, c10, 7 // register 0x7A
- bx lr
- mrc p14, 1, r0, c0, c11, 7 // register 0x7B
- bx lr
- mrc p14, 1, r0, c0, c12, 7 // register 0x7C
- bx lr
- mrc p14, 1, r0, c0, c13, 7 // register 0x7D
- bx lr
- mrc p14, 1, r0, c0, c14, 7 // register 0x7E
- bx lr
- mrc p14, 1, r0, c0, c15, 7 // register 0x7F
- bx lr
-
-.global etm_write_reg
-etm_write_reg:
- cmp r0, #0x7F
- bhi write_high
- ldr r2, =write_table
- add r2, r2, r0, lsl #3
- mov pc, r2
-
-write_high:
- cmp r0, #0xC0
- beq write_c0
- cmp r0, #0xC4
- beq write_c4
- bx lr
-
-write_c0:
- mcr p14, 1, r1, c1, c0, 4 // register 0xC0 (OS Lock Access Reg)
- bx lr
-
-write_c4:
- mcr p14, 1, r1, c1, c4, 4 // register 0xC4 (Powerdown Ctl Reg)
- bx lr
-
-write_table:
- mcr p14, 1, r1, c0, c0, 0 // register 0x00
- bx lr
- mcr p14, 1, r1, c0, c1, 0 // register 0x01
- bx lr
- mcr p14, 1, r1, c0, c2, 0 // register 0x02
- bx lr
- mcr p14, 1, r1, c0, c3, 0 // register 0x03
- bx lr
- mcr p14, 1, r1, c0, c4, 0 // register 0x04
- bx lr
- mcr p14, 1, r1, c0, c5, 0 // register 0x05
- bx lr
- mcr p14, 1, r1, c0, c6, 0 // register 0x06
- bx lr
- mcr p14, 1, r1, c0, c7, 0 // register 0x07
- bx lr
- mcr p14, 1, r1, c0, c8, 0 // register 0x08
- bx lr
- mcr p14, 1, r1, c0, c9, 0 // register 0x09
- bx lr
- mcr p14, 1, r1, c0, c10, 0 // register 0x0A
- bx lr
- mcr p14, 1, r1, c0, c11, 0 // register 0x0B
- bx lr
- mcr p14, 1, r1, c0, c12, 0 // register 0x0C
- bx lr
- mcr p14, 1, r1, c0, c13, 0 // register 0x0D
- bx lr
- mcr p14, 1, r1, c0, c14, 0 // register 0x0E
- bx lr
- mcr p14, 1, r1, c0, c15, 0 // register 0x0F
- bx lr
- mcr p14, 1, r1, c0, c0, 1 // register 0x10
- bx lr
- mcr p14, 1, r1, c0, c1, 1 // register 0x11
- bx lr
- mcr p14, 1, r1, c0, c2, 1 // register 0x12
- bx lr
- mcr p14, 1, r1, c0, c3, 1 // register 0x13
- bx lr
- mcr p14, 1, r1, c0, c4, 1 // register 0x14
- bx lr
- mcr p14, 1, r1, c0, c5, 1 // register 0x15
- bx lr
- mcr p14, 1, r1, c0, c6, 1 // register 0x16
- bx lr
- mcr p14, 1, r1, c0, c7, 1 // register 0x17
- bx lr
- mcr p14, 1, r1, c0, c8, 1 // register 0x18
- bx lr
- mcr p14, 1, r1, c0, c9, 1 // register 0x19
- bx lr
- mcr p14, 1, r1, c0, c10, 1 // register 0x1A
- bx lr
- mcr p14, 1, r1, c0, c11, 1 // register 0x1B
- bx lr
- mcr p14, 1, r1, c0, c12, 1 // register 0x1C
- bx lr
- mcr p14, 1, r1, c0, c13, 1 // register 0x1D
- bx lr
- mcr p14, 1, r1, c0, c14, 1 // register 0x1E
- bx lr
- mcr p14, 1, r1, c0, c15, 1 // register 0x1F
- bx lr
- mcr p14, 1, r1, c0, c0, 2 // register 0x20
- bx lr
- mcr p14, 1, r1, c0, c1, 2 // register 0x21
- bx lr
- mcr p14, 1, r1, c0, c2, 2 // register 0x22
- bx lr
- mcr p14, 1, r1, c0, c3, 2 // register 0x23
- bx lr
- mcr p14, 1, r1, c0, c4, 2 // register 0x24
- bx lr
- mcr p14, 1, r1, c0, c5, 2 // register 0x25
- bx lr
- mcr p14, 1, r1, c0, c6, 2 // register 0x26
- bx lr
- mcr p14, 1, r1, c0, c7, 2 // register 0x27
- bx lr
- mcr p14, 1, r1, c0, c8, 2 // register 0x28
- bx lr
- mcr p14, 1, r1, c0, c9, 2 // register 0x29
- bx lr
- mcr p14, 1, r1, c0, c10, 2 // register 0x2A
- bx lr
- mcr p14, 1, r1, c0, c11, 2 // register 0x2B
- bx lr
- mcr p14, 1, r1, c0, c12, 2 // register 0x2C
- bx lr
- mcr p14, 1, r1, c0, c13, 2 // register 0x2D
- bx lr
- mcr p14, 1, r1, c0, c14, 2 // register 0x2E
- bx lr
- mcr p14, 1, r1, c0, c15, 2 // register 0x2F
- bx lr
- mcr p14, 1, r1, c0, c0, 3 // register 0x30
- bx lr
- mcr p14, 1, r1, c0, c1, 3 // register 0x31
- bx lr
- mcr p14, 1, r1, c0, c2, 3 // register 0x32
- bx lr
- mcr p14, 1, r1, c0, c3, 3 // register 0x33
- bx lr
- mcr p14, 1, r1, c0, c4, 3 // register 0x34
- bx lr
- mcr p14, 1, r1, c0, c5, 3 // register 0x35
- bx lr
- mcr p14, 1, r1, c0, c6, 3 // register 0x36
- bx lr
- mcr p14, 1, r1, c0, c7, 3 // register 0x37
- bx lr
- mcr p14, 1, r1, c0, c8, 3 // register 0x38
- bx lr
- mcr p14, 1, r1, c0, c9, 3 // register 0x39
- bx lr
- mcr p14, 1, r1, c0, c10, 3 // register 0x3A
- bx lr
- mcr p14, 1, r1, c0, c11, 3 // register 0x3B
- bx lr
- mcr p14, 1, r1, c0, c12, 3 // register 0x3C
- bx lr
- mcr p14, 1, r1, c0, c13, 3 // register 0x3D
- bx lr
- mcr p14, 1, r1, c0, c14, 3 // register 0x3E
- bx lr
- mcr p14, 1, r1, c0, c15, 3 // register 0x3F
- bx lr
- mcr p14, 1, r1, c0, c0, 4 // register 0x40
- bx lr
- mcr p14, 1, r1, c0, c1, 4 // register 0x41
- bx lr
- mcr p14, 1, r1, c0, c2, 4 // register 0x42
- bx lr
- mcr p14, 1, r1, c0, c3, 4 // register 0x43
- bx lr
- mcr p14, 1, r1, c0, c4, 4 // register 0x44
- bx lr
- mcr p14, 1, r1, c0, c5, 4 // register 0x45
- bx lr
- mcr p14, 1, r1, c0, c6, 4 // register 0x46
- bx lr
- mcr p14, 1, r1, c0, c7, 4 // register 0x47
- bx lr
- mcr p14, 1, r1, c0, c8, 4 // register 0x48
- bx lr
- mcr p14, 1, r1, c0, c9, 4 // register 0x49
- bx lr
- mcr p14, 1, r1, c0, c10, 4 // register 0x4A
- bx lr
- mcr p14, 1, r1, c0, c11, 4 // register 0x4B
- bx lr
- mcr p14, 1, r1, c0, c12, 4 // register 0x4C
- bx lr
- mcr p14, 1, r1, c0, c13, 4 // register 0x4D
- bx lr
- mcr p14, 1, r1, c0, c14, 4 // register 0x4E
- bx lr
- mcr p14, 1, r1, c0, c15, 4 // register 0x4F
- bx lr
- mcr p14, 1, r1, c0, c0, 5 // register 0x50
- bx lr
- mcr p14, 1, r1, c0, c1, 5 // register 0x51
- bx lr
- mcr p14, 1, r1, c0, c2, 5 // register 0x52
- bx lr
- mcr p14, 1, r1, c0, c3, 5 // register 0x53
- bx lr
- mcr p14, 1, r1, c0, c4, 5 // register 0x54
- bx lr
- mcr p14, 1, r1, c0, c5, 5 // register 0x55
- bx lr
- mcr p14, 1, r1, c0, c6, 5 // register 0x56
- bx lr
- mcr p14, 1, r1, c0, c7, 5 // register 0x57
- bx lr
- mcr p14, 1, r1, c0, c8, 5 // register 0x58
- bx lr
- mcr p14, 1, r1, c0, c9, 5 // register 0x59
- bx lr
- mcr p14, 1, r1, c0, c10, 5 // register 0x5A
- bx lr
- mcr p14, 1, r1, c0, c11, 5 // register 0x5B
- bx lr
- mcr p14, 1, r1, c0, c12, 5 // register 0x5C
- bx lr
- mcr p14, 1, r1, c0, c13, 5 // register 0x5D
- bx lr
- mcr p14, 1, r1, c0, c14, 5 // register 0x5E
- bx lr
- mcr p14, 1, r1, c0, c15, 5 // register 0x5F
- bx lr
- mcr p14, 1, r1, c0, c0, 6 // register 0x60
- bx lr
- mcr p14, 1, r1, c0, c1, 6 // register 0x61
- bx lr
- mcr p14, 1, r1, c0, c2, 6 // register 0x62
- bx lr
- mcr p14, 1, r1, c0, c3, 6 // register 0x63
- bx lr
- mcr p14, 1, r1, c0, c4, 6 // register 0x64
- bx lr
- mcr p14, 1, r1, c0, c5, 6 // register 0x65
- bx lr
- mcr p14, 1, r1, c0, c6, 6 // register 0x66
- bx lr
- mcr p14, 1, r1, c0, c7, 6 // register 0x67
- bx lr
- mcr p14, 1, r1, c0, c8, 6 // register 0x68
- bx lr
- mcr p14, 1, r1, c0, c9, 6 // register 0x69
- bx lr
- mcr p14, 1, r1, c0, c10, 6 // register 0x6A
- bx lr
- mcr p14, 1, r1, c0, c11, 6 // register 0x6B
- bx lr
- mcr p14, 1, r1, c0, c12, 6 // register 0x6C
- bx lr
- mcr p14, 1, r1, c0, c13, 6 // register 0x6D
- bx lr
- mcr p14, 1, r1, c0, c14, 6 // register 0x6E
- bx lr
- mcr p14, 1, r1, c0, c15, 6 // register 0x6F
- bx lr
- mcr p14, 1, r1, c0, c0, 7 // register 0x70
- bx lr
- mcr p14, 1, r1, c0, c1, 7 // register 0x71
- bx lr
- mcr p14, 1, r1, c0, c2, 7 // register 0x72
- bx lr
- mcr p14, 1, r1, c0, c3, 7 // register 0x73
- bx lr
- mcr p14, 1, r1, c0, c4, 7 // register 0x74
- bx lr
- mcr p14, 1, r1, c0, c5, 7 // register 0x75
- bx lr
- mcr p14, 1, r1, c0, c6, 7 // register 0x76
- bx lr
- mcr p14, 1, r1, c0, c7, 7 // register 0x77
- bx lr
- mcr p14, 1, r1, c0, c8, 7 // register 0x78
- bx lr
- mcr p14, 1, r1, c0, c9, 7 // register 0x79
- bx lr
- mcr p14, 1, r1, c0, c10, 7 // register 0x7A
- bx lr
- mcr p14, 1, r1, c0, c11, 7 // register 0x7B
- bx lr
- mcr p14, 1, r1, c0, c12, 7 // register 0x7C
- bx lr
- mcr p14, 1, r1, c0, c13, 7 // register 0x7D
- bx lr
- mcr p14, 1, r1, c0, c14, 7 // register 0x7E
- bx lr
- mcr p14, 1, r1, c0, c15, 7 // register 0x7F
- bx lr
-
-.global l2tevselr0_write
-l2tevselr0_write:
- mcr p15, 3, r0, c15, c5, 2
- bx lr
-
-.global etm_save_reg
-etm_save_reg:
- ldr r3, =etm_state /* store state at etm_state */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
- and r2, r2, #15 /* What CPU am I */
- ldr r1, =MAX_ETM_STATE_SIZE
- mul r2, r2, r1
- add r3, r3, r2
-#endif
-
- /* save etm state */
- mrc p14, 1, r0, c1, c5, 4 /* read ETM PDSR to clear sticky bit */
- isb
- ldr r1, =0xc5ACCE55 /* set ETMOSLAR lock */
- mcr p14, 1, r1, c1, c0, 4
- isb
-
- mrc p14, 1, r1, c1, c2, 4 /* ETMOSSRR state register count */
- cmp r1, #(MAX_ETM_REGS) /* check for state overflow */
- movgt r1, #0 /* if not enough space, don't save */
- str r1,[r3],#4 /* save count for restore */
-
-1: cmp r1, #0
- mrcne p14, 1, r2, c1, c2, 4 /* ETMOSSRR state value */
- strne r2, [r3], #4 /* push value */
- subne r1, r1, #1
- bne 1b
-
- mcr p14, 1, r1, c1, c0, 4 /* r1 = 0, unlock ETMOSLAR */
- isb
-
- bx lr
-
-.global etm_restore_reg
-etm_restore_reg:
- /* restore debug registers after power collapse */
- ldr r3, =etm_state /* load state from etm_state */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
- and r2, r2, #15 /* What CPU am I */
- ldr r1, =MAX_ETM_STATE_SIZE
- mul r2, r2, r1
- add r3, r3, r2
-#endif
-
- /* restore etm state */
- mrc p14, 1, r0, c1, c5, 4 /* read ETM PDSR to clear sticky bit */
- isb
- ldr r1, =0xc5ACCE55 /* set ETMOSLAR lock */
- mcr p14, 1, r1, c1, c0, 4
- isb
-
- mrc p14, 1, r1, c1, c2, 4 /* ETMOSSRR dummy read (required)*/
- ldr r1, [r3], #4 /* load saved count */
- cmp r1, #0 /* skip if none stored */
- beq end_etm_restore_reg
-
-1: ldr r2,[r3],#4
- mcr p14, 1, r2, c1, c2, 4 /* ETMOSSRR write state value */
- subs r1, r1, #1
- bne 1b
-end_etm_restore_reg:
- mcr p14, 1, r1, c1, c0, 4 /* r1 = 0, unlock ETMOSLAR */
- isb
-
- bx lr
-
-
- .data
-
-etm_state:
- .space MAX_ETM_STATE_SIZE * NR_CPUS
diff --git a/arch/arm/mach-msm/cp14.h b/arch/arm/mach-msm/cp14.h
index 0946e07..9f7241e 100644
--- a/arch/arm/mach-msm/cp14.h
+++ b/arch/arm/mach-msm/cp14.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -10,10 +10,531 @@
* GNU General Public License for more details.
*/
+#ifndef _ARCH_ARM_MACH_MSM_CP14_H_
+#define _ARCH_ARM_MACH_MSM_CP14_H_
+
#include <linux/types.h>
-uint32_t etm_read_reg(uint32_t reg);
-void etm_write_reg(uint32_t reg, uint32_t val);
-void l2tevselr0_write(uint32_t val);
-void etm_save_reg(void);
-void etm_restore_reg(void);
+/* Accessors for CP14 registers */
+#define dbg_read(reg) RCP14_##reg()
+#define dbg_write(val, reg) WCP14_##reg(val)
+#define etm_read(reg) RCP14_##reg()
+#define etm_write(val, reg) WCP14_##reg(val)
+
+/* MRC14 and MCR14 */
+#define MRC14(op1, crn, crm, op2) \
+({ \
+uint32_t val; \
+asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
+val; \
+})
+
+#define MCR14(val, op1, crn, crm, op2) \
+({ \
+asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
+})
+
+/* Debug Registers
+ *
+ * Available only in DBGv7
+ * DBGECR, DBGDSCCR, DBGDSMCR, DBGDRCR
+ *
+ * Available only in DBGv7.1
+ * DBGBXVRm, DBGOSDLR, DBGDEVID2, DBGDEVID1
+ *
+ * Read only
+ * DBGDIDR, DBGDSCRint, DBGDTRRXint, DBGDRAR, DBGOSLSR, DBGOSSRR, DBGPRSR,
+ * DBGPRSR, DBGDSAR, DBGAUTHSTATUS, DBGDEVID2, DBGDEVID1, DBGDEVID
+ *
+ * Write only
+ * DBGDTRTXint, DBGOSLAR
+ */
+#define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
+#define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
+#define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
+#define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
+#define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
+#define RCP14_DBGECR() MRC14(0, c0, c9, 0)
+#define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
+#define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
+#define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
+#define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
+#define RCP14_DBGDTRTXext() MRC14(0, c0, c3, 2)
+#define RCP14_DBGDRCR() MRC14(0, c0, c4, 2)
+#define RCP14_DBGBVR0() MRC14(0, c0, c0, 4)
+#define RCP14_DBGBVR1() MRC14(0, c0, c1, 4)
+#define RCP14_DBGBVR2() MRC14(0, c0, c2, 4)
+#define RCP14_DBGBVR3() MRC14(0, c0, c3, 4)
+#define RCP14_DBGBVR4() MRC14(0, c0, c4, 4)
+#define RCP14_DBGBVR5() MRC14(0, c0, c5, 4)
+#define RCP14_DBGBVR6() MRC14(0, c0, c6, 4)
+#define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
+#define RCP14_DBGBVR8() MRC14(0, c0, c8, 4)
+#define RCP14_DBGBVR9() MRC14(0, c0, c9, 4)
+#define RCP14_DBGBVR10() MRC14(0, c0, c10, 4)
+#define RCP14_DBGBVR11() MRC14(0, c0, c11, 4)
+#define RCP14_DBGBVR12() MRC14(0, c0, c12, 4)
+#define RCP14_DBGBVR13() MRC14(0, c0, c13, 4)
+#define RCP14_DBGBVR14() MRC14(0, c0, c14, 4)
+#define RCP14_DBGBVR15() MRC14(0, c0, c15, 4)
+#define RCP14_DBGBCR0() MRC14(0, c0, c0, 5)
+#define RCP14_DBGBCR1() MRC14(0, c0, c1, 5)
+#define RCP14_DBGBCR2() MRC14(0, c0, c2, 5)
+#define RCP14_DBGBCR3() MRC14(0, c0, c3, 5)
+#define RCP14_DBGBCR4() MRC14(0, c0, c4, 5)
+#define RCP14_DBGBCR5() MRC14(0, c0, c5, 5)
+#define RCP14_DBGBCR6() MRC14(0, c0, c6, 5)
+#define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
+#define RCP14_DBGBCR8() MRC14(0, c0, c8, 5)
+#define RCP14_DBGBCR9() MRC14(0, c0, c9, 5)
+#define RCP14_DBGBCR10() MRC14(0, c0, c10, 5)
+#define RCP14_DBGBCR11() MRC14(0, c0, c11, 5)
+#define RCP14_DBGBCR12() MRC14(0, c0, c12, 5)
+#define RCP14_DBGBCR13() MRC14(0, c0, c13, 5)
+#define RCP14_DBGBCR14() MRC14(0, c0, c14, 5)
+#define RCP14_DBGBCR15() MRC14(0, c0, c15, 5)
+#define RCP14_DBGWVR0() MRC14(0, c0, c0, 6)
+#define RCP14_DBGWVR1() MRC14(0, c0, c1, 6)
+#define RCP14_DBGWVR2() MRC14(0, c0, c2, 6)
+#define RCP14_DBGWVR3() MRC14(0, c0, c3, 6)
+#define RCP14_DBGWVR4() MRC14(0, c0, c4, 6)
+#define RCP14_DBGWVR5() MRC14(0, c0, c5, 6)
+#define RCP14_DBGWVR6() MRC14(0, c0, c6, 6)
+#define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
+#define RCP14_DBGWVR8() MRC14(0, c0, c8, 6)
+#define RCP14_DBGWVR9() MRC14(0, c0, c9, 6)
+#define RCP14_DBGWVR10() MRC14(0, c0, c10, 6)
+#define RCP14_DBGWVR11() MRC14(0, c0, c11, 6)
+#define RCP14_DBGWVR12() MRC14(0, c0, c12, 6)
+#define RCP14_DBGWVR13() MRC14(0, c0, c13, 6)
+#define RCP14_DBGWVR14() MRC14(0, c0, c14, 6)
+#define RCP14_DBGWVR15() MRC14(0, c0, c15, 6)
+#define RCP14_DBGWCR0() MRC14(0, c0, c0, 7)
+#define RCP14_DBGWCR1() MRC14(0, c0, c1, 7)
+#define RCP14_DBGWCR2() MRC14(0, c0, c2, 7)
+#define RCP14_DBGWCR3() MRC14(0, c0, c3, 7)
+#define RCP14_DBGWCR4() MRC14(0, c0, c4, 7)
+#define RCP14_DBGWCR5() MRC14(0, c0, c5, 7)
+#define RCP14_DBGWCR6() MRC14(0, c0, c6, 7)
+#define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
+#define RCP14_DBGWCR8() MRC14(0, c0, c8, 7)
+#define RCP14_DBGWCR9() MRC14(0, c0, c9, 7)
+#define RCP14_DBGWCR10() MRC14(0, c0, c10, 7)
+#define RCP14_DBGWCR11() MRC14(0, c0, c11, 7)
+#define RCP14_DBGWCR12() MRC14(0, c0, c12, 7)
+#define RCP14_DBGWCR13() MRC14(0, c0, c13, 7)
+#define RCP14_DBGWCR14() MRC14(0, c0, c14, 7)
+#define RCP14_DBGWCR15() MRC14(0, c0, c15, 7)
+#define RCP14_DBGDRAR() MRC14(0, c1, c0, 0)
+#define RCP14_DBGBXVR0() MRC14(0, c1, c0, 1)
+#define RCP14_DBGBXVR1() MRC14(0, c1, c1, 1)
+#define RCP14_DBGBXVR2() MRC14(0, c1, c2, 1)
+#define RCP14_DBGBXVR3() MRC14(0, c1, c3, 1)
+#define RCP14_DBGBXVR4() MRC14(0, c1, c4, 1)
+#define RCP14_DBGBXVR5() MRC14(0, c1, c5, 1)
+#define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1)
+#define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
+#define RCP14_DBGBXVR8() MRC14(0, c1, c8, 1)
+#define RCP14_DBGBXVR9() MRC14(0, c1, c9, 1)
+#define RCP14_DBGBXVR10() MRC14(0, c1, c10, 1)
+#define RCP14_DBGBXVR11() MRC14(0, c1, c11, 1)
+#define RCP14_DBGBXVR12() MRC14(0, c1, c12, 1)
+#define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1)
+#define RCP14_DBGBXVR14() MRC14(0, c1, c14, 1)
+#define RCP14_DBGBXVR15() MRC14(0, c1, c15, 1)
+#define RCP14_DBGOSLSR() MRC14(0, c1, c1, 4)
+#define RCP14_DBGOSSRR() MRC14(0, c1, c2, 4)
+#define RCP14_DBGOSDLR() MRC14(0, c1, c3, 4)
+#define RCP14_DBGPRCR() MRC14(0, c1, c4, 4)
+#define RCP14_DBGPRSR() MRC14(0, c1, c5, 4)
+#define RCP14_DBGDSAR() MRC14(0, c2, c0, 0)
+#define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
+#define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
+#define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
+#define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
+#define RCP14_DBGDEVID2() MRC14(0, c7, c0, 7)
+#define RCP14_DBGDEVID1() MRC14(0, c7, c1, 7)
+#define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
+
+#define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0)
+#define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
+#define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0)
+#define WCP14_DBGECR(val) MCR14(val, 0, c0, c9, 0)
+#define WCP14_DBGDSCCR(val) MCR14(val, 0, c0, c10, 0)
+#define WCP14_DBGDSMCR(val) MCR14(val, 0, c0, c11, 0)
+#define WCP14_DBGDTRRXext(val) MCR14(val, 0, c0, c0, 2)
+#define WCP14_DBGDSCRext(val) MCR14(val, 0, c0, c2, 2)
+#define WCP14_DBGDTRTXext(val) MCR14(val, 0, c0, c3, 2)
+#define WCP14_DBGDRCR(val) MCR14(val, 0, c0, c4, 2)
+#define WCP14_DBGBVR0(val) MCR14(val, 0, c0, c0, 4)
+#define WCP14_DBGBVR1(val) MCR14(val, 0, c0, c1, 4)
+#define WCP14_DBGBVR2(val) MCR14(val, 0, c0, c2, 4)
+#define WCP14_DBGBVR3(val) MCR14(val, 0, c0, c3, 4)
+#define WCP14_DBGBVR4(val) MCR14(val, 0, c0, c4, 4)
+#define WCP14_DBGBVR5(val) MCR14(val, 0, c0, c5, 4)
+#define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
+#define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4)
+#define WCP14_DBGBVR8(val) MCR14(val, 0, c0, c8, 4)
+#define WCP14_DBGBVR9(val) MCR14(val, 0, c0, c9, 4)
+#define WCP14_DBGBVR10(val) MCR14(val, 0, c0, c10, 4)
+#define WCP14_DBGBVR11(val) MCR14(val, 0, c0, c11, 4)
+#define WCP14_DBGBVR12(val) MCR14(val, 0, c0, c12, 4)
+#define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4)
+#define WCP14_DBGBVR14(val) MCR14(val, 0, c0, c14, 4)
+#define WCP14_DBGBVR15(val) MCR14(val, 0, c0, c15, 4)
+#define WCP14_DBGBCR0(val) MCR14(val, 0, c0, c0, 5)
+#define WCP14_DBGBCR1(val) MCR14(val, 0, c0, c1, 5)
+#define WCP14_DBGBCR2(val) MCR14(val, 0, c0, c2, 5)
+#define WCP14_DBGBCR3(val) MCR14(val, 0, c0, c3, 5)
+#define WCP14_DBGBCR4(val) MCR14(val, 0, c0, c4, 5)
+#define WCP14_DBGBCR5(val) MCR14(val, 0, c0, c5, 5)
+#define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
+#define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5)
+#define WCP14_DBGBCR8(val) MCR14(val, 0, c0, c8, 5)
+#define WCP14_DBGBCR9(val) MCR14(val, 0, c0, c9, 5)
+#define WCP14_DBGBCR10(val) MCR14(val, 0, c0, c10, 5)
+#define WCP14_DBGBCR11(val) MCR14(val, 0, c0, c11, 5)
+#define WCP14_DBGBCR12(val) MCR14(val, 0, c0, c12, 5)
+#define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5)
+#define WCP14_DBGBCR14(val) MCR14(val, 0, c0, c14, 5)
+#define WCP14_DBGBCR15(val) MCR14(val, 0, c0, c15, 5)
+#define WCP14_DBGWVR0(val) MCR14(val, 0, c0, c0, 6)
+#define WCP14_DBGWVR1(val) MCR14(val, 0, c0, c1, 6)
+#define WCP14_DBGWVR2(val) MCR14(val, 0, c0, c2, 6)
+#define WCP14_DBGWVR3(val) MCR14(val, 0, c0, c3, 6)
+#define WCP14_DBGWVR4(val) MCR14(val, 0, c0, c4, 6)
+#define WCP14_DBGWVR5(val) MCR14(val, 0, c0, c5, 6)
+#define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6, 6)
+#define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6)
+#define WCP14_DBGWVR8(val) MCR14(val, 0, c0, c8, 6)
+#define WCP14_DBGWVR9(val) MCR14(val, 0, c0, c9, 6)
+#define WCP14_DBGWVR10(val) MCR14(val, 0, c0, c10, 6)
+#define WCP14_DBGWVR11(val) MCR14(val, 0, c0, c11, 6)
+#define WCP14_DBGWVR12(val) MCR14(val, 0, c0, c12, 6)
+#define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6)
+#define WCP14_DBGWVR14(val) MCR14(val, 0, c0, c14, 6)
+#define WCP14_DBGWVR15(val) MCR14(val, 0, c0, c15, 6)
+#define WCP14_DBGWCR0(val) MCR14(val, 0, c0, c0, 7)
+#define WCP14_DBGWCR1(val) MCR14(val, 0, c0, c1, 7)
+#define WCP14_DBGWCR2(val) MCR14(val, 0, c0, c2, 7)
+#define WCP14_DBGWCR3(val) MCR14(val, 0, c0, c3, 7)
+#define WCP14_DBGWCR4(val) MCR14(val, 0, c0, c4, 7)
+#define WCP14_DBGWCR5(val) MCR14(val, 0, c0, c5, 7)
+#define WCP14_DBGWCR6(val) MCR14(val, 0, c0, c6, 7)
+#define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7)
+#define WCP14_DBGWCR8(val) MCR14(val, 0, c0, c8, 7)
+#define WCP14_DBGWCR9(val) MCR14(val, 0, c0, c9, 7)
+#define WCP14_DBGWCR10(val) MCR14(val, 0, c0, c10, 7)
+#define WCP14_DBGWCR11(val) MCR14(val, 0, c0, c11, 7)
+#define WCP14_DBGWCR12(val) MCR14(val, 0, c0, c12, 7)
+#define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7)
+#define WCP14_DBGWCR14(val) MCR14(val, 0, c0, c14, 7)
+#define WCP14_DBGWCR15(val) MCR14(val, 0, c0, c15, 7)
+#define WCP14_DBGBXVR0(val) MCR14(val, 0, c1, c0, 1)
+#define WCP14_DBGBXVR1(val) MCR14(val, 0, c1, c1, 1)
+#define WCP14_DBGBXVR2(val) MCR14(val, 0, c1, c2, 1)
+#define WCP14_DBGBXVR3(val) MCR14(val, 0, c1, c3, 1)
+#define WCP14_DBGBXVR4(val) MCR14(val, 0, c1, c4, 1)
+#define WCP14_DBGBXVR5(val) MCR14(val, 0, c1, c5, 1)
+#define WCP14_DBGBXVR6(val) MCR14(val, 0, c1, c6, 1)
+#define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1)
+#define WCP14_DBGBXVR8(val) MCR14(val, 0, c1, c8, 1)
+#define WCP14_DBGBXVR9(val) MCR14(val, 0, c1, c9, 1)
+#define WCP14_DBGBXVR10(val) MCR14(val, 0, c1, c10, 1)
+#define WCP14_DBGBXVR11(val) MCR14(val, 0, c1, c11, 1)
+#define WCP14_DBGBXVR12(val) MCR14(val, 0, c1, c12, 1)
+#define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1)
+#define WCP14_DBGBXVR14(val) MCR14(val, 0, c1, c14, 1)
+#define WCP14_DBGBXVR15(val) MCR14(val, 0, c1, c15, 1)
+#define WCP14_DBGOSLAR(val) MCR14(val, 0, c1, c0, 4)
+#define WCP14_DBGOSSRR(val) MCR14(val, 0, c1, c2, 4)
+#define WCP14_DBGOSDLR(val) MCR14(val, 0, c1, c3, 4)
+#define WCP14_DBGPRCR(val) MCR14(val, 0, c1, c4, 4)
+#define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4)
+#define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6)
+#define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6)
+
+/* ETM Registers
+ *
+ * Available only in ETMv3.3, 3.4, 3.5
+ * ETMASICCR, ETMTECR2, ETMFFRR, ETMVDEVR, ETMVDCR1, ETMVDCR2, ETMVDCR3,
+ * ETMDCVRn, ETMDCMRn
+ *
+ * Available only in ETMv3.5 as read only
+ * ETMIDR2
+ *
+ * Available only in ETMv3.5, PFTv1.0, 1.1
+ * ETMTSEVR, ETMVMIDCVR, ETMPDCR
+ *
+ * Read only
+ * ETMCCR, ETMSCR, ETMIDR, ETMCCER, ETMOSLSR
+ * ETMLSR, ETMAUTHSTATUS, ETMDEVID, ETMDEVTYPE, ETMPIDR4, ETMPIDR5, ETMPIDR6,
+ * ETMPIDR7, ETMPIDR0, ETMPIDR1, ETMPIDR2, ETMPIDR2, ETMPIDR3, ETMCIDR0,
+ * ETMCIDR1, ETMCIDR2, ETMCIDR3
+ *
+ * Write only
+ * ETMOSLAR, ETMLAR
+ * Note: ETMCCER[11] controls WO nature of certain regs. Refer ETM arch spec.
+ */
+#define RCP14_ETMCR() MRC14(1, c0, c0, 0)
+#define RCP14_ETMCCR() MRC14(1, c0, c1, 0)
+#define RCP14_ETMTRIGGER() MRC14(1, c0, c2, 0)
+#define RCP14_ETMASICCR() MRC14(1, c0, c3, 0)
+#define RCP14_ETMSR() MRC14(1, c0, c4, 0)
+#define RCP14_ETMSCR() MRC14(1, c0, c5, 0)
+#define RCP14_ETMTSSCR() MRC14(1, c0, c6, 0)
+#define RCP14_ETMTECR2() MRC14(1, c0, c7, 0)
+#define RCP14_ETMTEEVR() MRC14(1, c0, c8, 0)
+#define RCP14_ETMTECR1() MRC14(1, c0, c9, 0)
+#define RCP14_ETMFFRR() MRC14(1, c0, c10, 0)
+#define RCP14_ETMFFLR() MRC14(1, c0, c11, 0)
+#define RCP14_ETMVDEVR() MRC14(1, c0, c12, 0)
+#define RCP14_ETMVDCR1() MRC14(1, c0, c13, 0)
+#define RCP14_ETMVDCR2() MRC14(1, c0, c14, 0)
+#define RCP14_ETMVDCR3() MRC14(1, c0, c15, 0)
+#define RCP14_ETMACVR0() MRC14(1, c0, c0, 1)
+#define RCP14_ETMACVR1() MRC14(1, c0, c1, 1)
+#define RCP14_ETMACVR2() MRC14(1, c0, c2, 1)
+#define RCP14_ETMACVR3() MRC14(1, c0, c3, 1)
+#define RCP14_ETMACVR4() MRC14(1, c0, c4, 1)
+#define RCP14_ETMACVR5() MRC14(1, c0, c5, 1)
+#define RCP14_ETMACVR6() MRC14(1, c0, c6, 1)
+#define RCP14_ETMACVR7() MRC14(1, c0, c7, 1)
+#define RCP14_ETMACVR8() MRC14(1, c0, c8, 1)
+#define RCP14_ETMACVR9() MRC14(1, c0, c9, 1)
+#define RCP14_ETMACVR10() MRC14(1, c0, c10, 1)
+#define RCP14_ETMACVR11() MRC14(1, c0, c11, 1)
+#define RCP14_ETMACVR12() MRC14(1, c0, c12, 1)
+#define RCP14_ETMACVR13() MRC14(1, c0, c13, 1)
+#define RCP14_ETMACVR14() MRC14(1, c0, c14, 1)
+#define RCP14_ETMACVR15() MRC14(1, c0, c15, 1)
+#define RCP14_ETMACTR0() MRC14(1, c0, c0, 2)
+#define RCP14_ETMACTR1() MRC14(1, c0, c1, 2)
+#define RCP14_ETMACTR2() MRC14(1, c0, c2, 2)
+#define RCP14_ETMACTR3() MRC14(1, c0, c3, 2)
+#define RCP14_ETMACTR4() MRC14(1, c0, c4, 2)
+#define RCP14_ETMACTR5() MRC14(1, c0, c5, 2)
+#define RCP14_ETMACTR6() MRC14(1, c0, c6, 2)
+#define RCP14_ETMACTR7() MRC14(1, c0, c7, 2)
+#define RCP14_ETMACTR8() MRC14(1, c0, c8, 2)
+#define RCP14_ETMACTR9() MRC14(1, c0, c9, 2)
+#define RCP14_ETMACTR10() MRC14(1, c0, c10, 2)
+#define RCP14_ETMACTR11() MRC14(1, c0, c11, 2)
+#define RCP14_ETMACTR12() MRC14(1, c0, c12, 2)
+#define RCP14_ETMACTR13() MRC14(1, c0, c13, 2)
+#define RCP14_ETMACTR14() MRC14(1, c0, c14, 2)
+#define RCP14_ETMACTR15() MRC14(1, c0, c15, 2)
+#define RCP14_ETMDCVR0() MRC14(1, c0, c0, 3)
+#define RCP14_ETMDCVR1() MRC14(1, c0, c1, 3)
+#define RCP14_ETMDCVR2() MRC14(1, c0, c2, 3)
+#define RCP14_ETMDCVR3() MRC14(1, c0, c3, 3)
+#define RCP14_ETMDCVR4() MRC14(1, c0, c4, 3)
+#define RCP14_ETMDCVR5() MRC14(1, c0, c5, 3)
+#define RCP14_ETMDCVR6() MRC14(1, c0, c6, 3)
+#define RCP14_ETMDCVR7() MRC14(1, c0, c7, 3)
+#define RCP14_ETMDCMR0() MRC14(1, c0, c0, 4)
+#define RCP14_ETMDCMR1() MRC14(1, c0, c1, 4)
+#define RCP14_ETMDCMR2() MRC14(1, c0, c2, 4)
+#define RCP14_ETMDCMR3() MRC14(1, c0, c3, 4)
+#define RCP14_ETMDCMR4() MRC14(1, c0, c4, 4)
+#define RCP14_ETMDCMR5() MRC14(1, c0, c5, 4)
+#define RCP14_ETMDCMR6() MRC14(1, c0, c6, 4)
+#define RCP14_ETMDCMR7() MRC14(1, c0, c7, 4)
+#define RCP14_ETMCNTRLDVR0() MRC14(1, c0, c0, 5)
+#define RCP14_ETMCNTRLDVR1() MRC14(1, c0, c1, 5)
+#define RCP14_ETMCNTRLDVR2() MRC14(1, c0, c2, 5)
+#define RCP14_ETMCNTRLDVR3() MRC14(1, c0, c3, 5)
+#define RCP14_ETMCNTENR0() MRC14(1, c0, c4, 5)
+#define RCP14_ETMCNTENR1() MRC14(1, c0, c5, 5)
+#define RCP14_ETMCNTENR2() MRC14(1, c0, c6, 5)
+#define RCP14_ETMCNTENR3() MRC14(1, c0, c7, 5)
+#define RCP14_ETMCNTRLDEVR0() MRC14(1, c0, c8, 5)
+#define RCP14_ETMCNTRLDEVR1() MRC14(1, c0, c9, 5)
+#define RCP14_ETMCNTRLDEVR2() MRC14(1, c0, c10, 5)
+#define RCP14_ETMCNTRLDEVR3() MRC14(1, c0, c11, 5)
+#define RCP14_ETMCNTVR0() MRC14(1, c0, c12, 5)
+#define RCP14_ETMCNTVR1() MRC14(1, c0, c13, 5)
+#define RCP14_ETMCNTVR2() MRC14(1, c0, c14, 5)
+#define RCP14_ETMCNTVR3() MRC14(1, c0, c15, 5)
+#define RCP14_ETMSQ12EVR() MRC14(1, c0, c0, 6)
+#define RCP14_ETMSQ21EVR() MRC14(1, c0, c1, 6)
+#define RCP14_ETMSQ23EVR() MRC14(1, c0, c2, 6)
+#define RCP14_ETMSQ31EVR() MRC14(1, c0, c3, 6)
+#define RCP14_ETMSQ32EVR() MRC14(1, c0, c4, 6)
+#define RCP14_ETMSQ13EVR() MRC14(1, c0, c5, 6)
+#define RCP14_ETMSQR() MRC14(1, c0, c7, 6)
+#define RCP14_ETMEXTOUTEVR0() MRC14(1, c0, c8, 6)
+#define RCP14_ETMEXTOUTEVR1() MRC14(1, c0, c9, 6)
+#define RCP14_ETMEXTOUTEVR2() MRC14(1, c0, c10, 6)
+#define RCP14_ETMEXTOUTEVR3() MRC14(1, c0, c11, 6)
+#define RCP14_ETMCIDCVR0() MRC14(1, c0, c12, 6)
+#define RCP14_ETMCIDCVR1() MRC14(1, c0, c13, 6)
+#define RCP14_ETMCIDCVR2() MRC14(1, c0, c14, 6)
+#define RCP14_ETMCIDCMR() MRC14(1, c0, c15, 6)
+#define RCP14_ETMIMPSPEC0() MRC14(1, c0, c0, 7)
+#define RCP14_ETMIMPSPEC1() MRC14(1, c0, c1, 7)
+#define RCP14_ETMIMPSPEC2() MRC14(1, c0, c2, 7)
+#define RCP14_ETMIMPSPEC3() MRC14(1, c0, c3, 7)
+#define RCP14_ETMIMPSPEC4() MRC14(1, c0, c4, 7)
+#define RCP14_ETMIMPSPEC5() MRC14(1, c0, c5, 7)
+#define RCP14_ETMIMPSPEC6() MRC14(1, c0, c6, 7)
+#define RCP14_ETMIMPSPEC7() MRC14(1, c0, c7, 7)
+#define RCP14_ETMSYNCFR() MRC14(1, c0, c8, 7)
+#define RCP14_ETMIDR() MRC14(1, c0, c9, 7)
+#define RCP14_ETMCCER() MRC14(1, c0, c10, 7)
+#define RCP14_ETMEXTINSELR() MRC14(1, c0, c11, 7)
+#define RCP14_ETMTESSEICR() MRC14(1, c0, c12, 7)
+#define RCP14_ETMEIBCR() MRC14(1, c0, c13, 7)
+#define RCP14_ETMTSEVR() MRC14(1, c0, c14, 7)
+#define RCP14_ETMAUXCR() MRC14(1, c0, c15, 7)
+#define RCP14_ETMTRACEIDR() MRC14(1, c1, c0, 0)
+#define RCP14_ETMIDR2() MRC14(1, c1, c2, 0)
+#define RCP14_ETMVMIDCVR() MRC14(1, c1, c1, 0)
+#define RCP14_ETMOSLSR() MRC14(1, c1, c1, 4)
+/* not available in PFTv1.1 */
+#define RCP14_ETMOSSRR() MRC14(1, c1, c2, 4)
+#define RCP14_ETMPDCR() MRC14(1, c1, c4, 4)
+#define RCP14_ETMPDSR() MRC14(1, c1, c5, 4)
+#define RCP14_ETMITCTRL() MRC14(1, c7, c0, 4)
+#define RCP14_ETMCLAIMSET() MRC14(1, c7, c8, 6)
+#define RCP14_ETMCLAIMCLR() MRC14(1, c7, c9, 6)
+#define RCP14_ETMLSR() MRC14(1, c7, c13, 6)
+#define RCP14_ETMAUTHSTATUS() MRC14(1, c7, c14, 6)
+#define RCP14_ETMDEVID() MRC14(1, c7, c2, 7)
+#define RCP14_ETMDEVTYPE() MRC14(1, c7, c3, 7)
+#define RCP14_ETMPIDR4() MRC14(1, c7, c4, 7)
+#define RCP14_ETMPIDR5() MRC14(1, c7, c5, 7)
+#define RCP14_ETMPIDR6() MRC14(1, c7, c6, 7)
+#define RCP14_ETMPIDR7() MRC14(1, c7, c7, 7)
+#define RCP14_ETMPIDR0() MRC14(1, c7, c8, 7)
+#define RCP14_ETMPIDR1() MRC14(1, c7, c9, 7)
+#define RCP14_ETMPIDR2() MRC14(1, c7, c10, 7)
+#define RCP14_ETMPIDR3() MRC14(1, c7, c11, 7)
+#define RCP14_ETMCIDR0() MRC14(1, c7, c12, 7)
+#define RCP14_ETMCIDR1() MRC14(1, c7, c13, 7)
+#define RCP14_ETMCIDR2() MRC14(1, c7, c14, 7)
+#define RCP14_ETMCIDR3() MRC14(1, c7, c15, 7)
+
+#define WCP14_ETMCR(val) MCR14(val, 1, c0, c0, 0)
+#define WCP14_ETMTRIGGER(val) MCR14(val, 1, c0, c2, 0)
+#define WCP14_ETMASICCR(val) MCR14(val, 1, c0, c3, 0)
+#define WCP14_ETMSR(val) MCR14(val, 1, c0, c4, 0)
+#define WCP14_ETMTSSCR(val) MCR14(val, 1, c0, c6, 0)
+#define WCP14_ETMTECR2(val) MCR14(val, 1, c0, c7, 0)
+#define WCP14_ETMTEEVR(val) MCR14(val, 1, c0, c8, 0)
+#define WCP14_ETMTECR1(val) MCR14(val, 1, c0, c9, 0)
+#define WCP14_ETMFFRR(val) MCR14(val, 1, c0, c10, 0)
+#define WCP14_ETMFFLR(val) MCR14(val, 1, c0, c11, 0)
+#define WCP14_ETMVDEVR(val) MCR14(val, 1, c0, c12, 0)
+#define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0)
+#define WCP14_ETMVDCR2(val) MCR14(val, 1, c0, c14, 0)
+#define WCP14_ETMVDCR3(val) MCR14(val, 1, c0, c15, 0)
+#define WCP14_ETMACVR0(val) MCR14(val, 1, c0, c0, 1)
+#define WCP14_ETMACVR1(val) MCR14(val, 1, c0, c1, 1)
+#define WCP14_ETMACVR2(val) MCR14(val, 1, c0, c2, 1)
+#define WCP14_ETMACVR3(val) MCR14(val, 1, c0, c3, 1)
+#define WCP14_ETMACVR4(val) MCR14(val, 1, c0, c4, 1)
+#define WCP14_ETMACVR5(val) MCR14(val, 1, c0, c5, 1)
+#define WCP14_ETMACVR6(val) MCR14(val, 1, c0, c6, 1)
+#define WCP14_ETMACVR7(val) MCR14(val, 1, c0, c7, 1)
+#define WCP14_ETMACVR8(val) MCR14(val, 1, c0, c8, 1)
+#define WCP14_ETMACVR9(val) MCR14(val, 1, c0, c9, 1)
+#define WCP14_ETMACVR10(val) MCR14(val, 1, c0, c10, 1)
+#define WCP14_ETMACVR11(val) MCR14(val, 1, c0, c11, 1)
+#define WCP14_ETMACVR12(val) MCR14(val, 1, c0, c12, 1)
+#define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1)
+#define WCP14_ETMACVR14(val) MCR14(val, 1, c0, c14, 1)
+#define WCP14_ETMACVR15(val) MCR14(val, 1, c0, c15, 1)
+#define WCP14_ETMACTR0(val) MCR14(val, 1, c0, c0, 2)
+#define WCP14_ETMACTR1(val) MCR14(val, 1, c0, c1, 2)
+#define WCP14_ETMACTR2(val) MCR14(val, 1, c0, c2, 2)
+#define WCP14_ETMACTR3(val) MCR14(val, 1, c0, c3, 2)
+#define WCP14_ETMACTR4(val) MCR14(val, 1, c0, c4, 2)
+#define WCP14_ETMACTR5(val) MCR14(val, 1, c0, c5, 2)
+#define WCP14_ETMACTR6(val) MCR14(val, 1, c0, c6, 2)
+#define WCP14_ETMACTR7(val) MCR14(val, 1, c0, c7, 2)
+#define WCP14_ETMACTR8(val) MCR14(val, 1, c0, c8, 2)
+#define WCP14_ETMACTR9(val) MCR14(val, 1, c0, c9, 2)
+#define WCP14_ETMACTR10(val) MCR14(val, 1, c0, c10, 2)
+#define WCP14_ETMACTR11(val) MCR14(val, 1, c0, c11, 2)
+#define WCP14_ETMACTR12(val) MCR14(val, 1, c0, c12, 2)
+#define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2)
+#define WCP14_ETMACTR14(val) MCR14(val, 1, c0, c14, 2)
+#define WCP14_ETMACTR15(val) MCR14(val, 1, c0, c15, 2)
+#define WCP14_ETMDCVR0(val) MCR14(val, 1, c0, c0, 3)
+#define WCP14_ETMDCVR1(val) MCR14(val, 1, c0, c1, 3)
+#define WCP14_ETMDCVR2(val) MCR14(val, 1, c0, c2, 3)
+#define WCP14_ETMDCVR3(val) MCR14(val, 1, c0, c3, 3)
+#define WCP14_ETMDCVR4(val) MCR14(val, 1, c0, c4, 3)
+#define WCP14_ETMDCVR5(val) MCR14(val, 1, c0, c5, 3)
+#define WCP14_ETMDCVR6(val) MCR14(val, 1, c0, c6, 3)
+#define WCP14_ETMDCVR7(val) MCR14(val, 1, c0, c7, 3)
+#define WCP14_ETMDCMR0(val) MCR14(val, 1, c0, c0, 4)
+#define WCP14_ETMDCMR1(val) MCR14(val, 1, c0, c1, 4)
+#define WCP14_ETMDCMR2(val) MCR14(val, 1, c0, c2, 4)
+#define WCP14_ETMDCMR3(val) MCR14(val, 1, c0, c3, 4)
+#define WCP14_ETMDCMR4(val) MCR14(val, 1, c0, c4, 4)
+#define WCP14_ETMDCMR5(val) MCR14(val, 1, c0, c5, 4)
+#define WCP14_ETMDCMR6(val) MCR14(val, 1, c0, c6, 4)
+#define WCP14_ETMDCMR7(val) MCR14(val, 1, c0, c7, 4)
+#define WCP14_ETMCNTRLDVR0(val) MCR14(val, 1, c0, c0, 5)
+#define WCP14_ETMCNTRLDVR1(val) MCR14(val, 1, c0, c1, 5)
+#define WCP14_ETMCNTRLDVR2(val) MCR14(val, 1, c0, c2, 5)
+#define WCP14_ETMCNTRLDVR3(val) MCR14(val, 1, c0, c3, 5)
+#define WCP14_ETMCNTENR0(val) MCR14(val, 1, c0, c4, 5)
+#define WCP14_ETMCNTENR1(val) MCR14(val, 1, c0, c5, 5)
+#define WCP14_ETMCNTENR2(val) MCR14(val, 1, c0, c6, 5)
+#define WCP14_ETMCNTENR3(val) MCR14(val, 1, c0, c7, 5)
+#define WCP14_ETMCNTRLDEVR0(val) MCR14(val, 1, c0, c8, 5)
+#define WCP14_ETMCNTRLDEVR1(val) MCR14(val, 1, c0, c9, 5)
+#define WCP14_ETMCNTRLDEVR2(val) MCR14(val, 1, c0, c10, 5)
+#define WCP14_ETMCNTRLDEVR3(val) MCR14(val, 1, c0, c11, 5)
+#define WCP14_ETMCNTVR0(val) MCR14(val, 1, c0, c12, 5)
+#define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5)
+#define WCP14_ETMCNTVR2(val) MCR14(val, 1, c0, c14, 5)
+#define WCP14_ETMCNTVR3(val) MCR14(val, 1, c0, c15, 5)
+#define WCP14_ETMSQ12EVR(val) MCR14(val, 1, c0, c0, 6)
+#define WCP14_ETMSQ21EVR(val) MCR14(val, 1, c0, c1, 6)
+#define WCP14_ETMSQ23EVR(val) MCR14(val, 1, c0, c2, 6)
+#define WCP14_ETMSQ31EVR(val) MCR14(val, 1, c0, c3, 6)
+#define WCP14_ETMSQ32EVR(val) MCR14(val, 1, c0, c4, 6)
+#define WCP14_ETMSQ13EVR(val) MCR14(val, 1, c0, c5, 6)
+#define WCP14_ETMSQR(val) MCR14(val, 1, c0, c7, 6)
+#define WCP14_ETMEXTOUTEVR0(val) MCR14(val, 1, c0, c8, 6)
+#define WCP14_ETMEXTOUTEVR1(val) MCR14(val, 1, c0, c9, 6)
+#define WCP14_ETMEXTOUTEVR2(val) MCR14(val, 1, c0, c10, 6)
+#define WCP14_ETMEXTOUTEVR3(val) MCR14(val, 1, c0, c11, 6)
+#define WCP14_ETMCIDCVR0(val) MCR14(val, 1, c0, c12, 6)
+#define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6)
+#define WCP14_ETMCIDCVR2(val) MCR14(val, 1, c0, c14, 6)
+#define WCP14_ETMCIDCMR(val) MCR14(val, 1, c0, c15, 6)
+#define WCP14_ETMIMPSPEC0(val) MCR14(val, 1, c0, c0, 7)
+#define WCP14_ETMIMPSPEC1(val) MCR14(val, 1, c0, c1, 7)
+#define WCP14_ETMIMPSPEC2(val) MCR14(val, 1, c0, c2, 7)
+#define WCP14_ETMIMPSPEC3(val) MCR14(val, 1, c0, c3, 7)
+#define WCP14_ETMIMPSPEC4(val) MCR14(val, 1, c0, c4, 7)
+#define WCP14_ETMIMPSPEC5(val) MCR14(val, 1, c0, c5, 7)
+#define WCP14_ETMIMPSPEC6(val) MCR14(val, 1, c0, c6, 7)
+#define WCP14_ETMIMPSPEC7(val) MCR14(val, 1, c0, c7, 7)
+/* can be read only in ETMv3.4, ETMv3.5 */
+#define WCP14_ETMSYNCFR(val) MCR14(val, 1, c0, c8, 7)
+#define WCP14_ETMEXTINSELR(val) MCR14(val, 1, c0, c11, 7)
+#define WCP14_ETMTESSEICR(val) MCR14(val, 1, c0, c12, 7)
+#define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7)
+#define WCP14_ETMTSEVR(val) MCR14(val, 1, c0, c14, 7)
+#define WCP14_ETMAUXCR(val) MCR14(val, 1, c0, c15, 7)
+#define WCP14_ETMTRACEIDR(val) MCR14(val, 1, c1, c0, 0)
+#define WCP14_ETMIDR2(val) MCR14(val, 1, c1, c2, 0)
+#define WCP14_ETMVMIDCVR(val) MCR14(val, 1, c1, c1, 0)
+#define WCP14_ETMOSLAR(val) MCR14(val, 1, c1, c0, 4)
+/* not available in PFTv1.1 */
+#define WCP14_ETMOSSRR(val) MCR14(val, 1, c1, c2, 4)
+#define WCP14_ETMPDCR(val) MCR14(val, 1, c1, c4, 4)
+#define WCP14_ETMPDSR(val) MCR14(val, 1, c1, c5, 4)
+#define WCP14_ETMITCTRL(val) MCR14(val, 1, c7, c0, 4)
+#define WCP14_ETMCLAIMSET(val) MCR14(val, 1, c7, c8, 6)
+#define WCP14_ETMCLAIMCLR(val) MCR14(val, 1, c7, c9, 6)
+/* writes to this from CP14 interface are ignored */
+#define WCP14_ETMLAR(val) MCR14(val, 1, c7, c12, 6)
+
+#endif
diff --git a/arch/arm/mach-msm/devices-8960.c b/arch/arm/mach-msm/devices-8960.c
index 7f92bbe..4fa3e92 100644
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -2597,7 +2597,6 @@
#define MSM_ETB_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x1000)
#define MSM_TPIU_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x3000)
#define MSM_FUNNEL_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x4000)
-#define MSM_DEBUG_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x10000)
#define MSM_PTM_PHYS_BASE (MSM_QDSS_PHYS_BASE + 0x1C000)
static struct resource msm_etb_resources[] = {
@@ -2645,26 +2644,6 @@
.resource = msm_funnel_resources,
};
-static struct resource msm_debug_resources[] = {
- {
- .start = MSM_DEBUG_PHYS_BASE,
- .end = MSM_DEBUG_PHYS_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = MSM_DEBUG_PHYS_BASE + (SZ_4K * 2),
- .end = MSM_DEBUG_PHYS_BASE + (SZ_4K * 2) + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device msm_debug_device = {
- .name = "msm_debug",
- .id = 0,
- .num_resources = ARRAY_SIZE(msm_debug_resources),
- .resource = msm_debug_resources,
-};
-
static struct resource msm_ptm_resources[] = {
{
.start = MSM_PTM_PHYS_BASE,
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 8a9c9fc..6d8d393 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -1,7 +1,7 @@
/* linux/arch/arm/mach-msm/devices.h
*
* Copyright (C) 2008 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -262,6 +262,5 @@
extern struct platform_device msm_etb_device;
extern struct platform_device msm_tpiu_device;
extern struct platform_device msm_funnel_device;
-extern struct platform_device msm_debug_device;
extern struct platform_device msm_ptm_device;
#endif
diff --git a/arch/arm/mach-msm/etm.c b/arch/arm/mach-msm/etm.c
index 81c0478..bee0975 100644
--- a/arch/arm/mach-msm/etm.c
+++ b/arch/arm/mach-msm/etm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -28,8 +28,6 @@
#include "cp14.h"
#define LOG_BUF_LEN 32768
-#define ETM_NUM_REGS 128
-#define ETB_NUM_REGS 9
/* each slot is 4 bytes, 8kb total */
#define ETB_RAM_SLOTS 2048
@@ -37,14 +35,16 @@
#define ETM_DUMP_MSG_ID 0x000A6960
#define ETB_DUMP_MSG_ID 0x000A6961
-/* ETM Registers */
-#define ETM_REG_CONTROL 0x00
-#define ETM_REG_STATUS 0x04
-#define ETB_REG_CONTROL 0x71
-#define ETB_REG_STATUS 0x72
-#define ETB_REG_COUNT 0x73
-#define ETB_REG_ADDRESS 0x74
-#define ETB_REG_DATA 0x75
+/* ETB Registers */
+#define ETB_REG_CONTROL ETMIMPSPEC1
+#define ETB_REG_STATUS ETMIMPSPEC2
+#define ETB_REG_COUNT ETMIMPSPEC3
+#define ETB_REG_ADDRESS ETMIMPSPEC4
+#define ETB_REG_DATA ETMIMPSPEC5
+
+/* Having etb macro accessors allows macro expansion for ETB reg defines */
+#define etb_read(reg) etm_read(reg)
+#define etb_write(val, reg) etm_write(val, reg)
/* Bitmasks for the ETM control register */
#define ETM_CONTROL_POWERDOWN 0x00000001
@@ -186,6 +186,41 @@
.etb_init_ptr = 0x00000010,
};
+/* ETM clock is derived from the processor clock and gets enabled on a
+ * logical OR of below items on Scorpion:
+ * 1.CPMR[ETMCLKEN] is set
+ * 2.ETM is not idle. Also means ETMCR[PD] is 0
+ * 3.Reset is asserted (core or debug)
+ * 4.MRC/MCR to ETM reg (CP14 access)
+ * 5.Debugger access to a ETM register in the core power domain
+ *
+ * 1. and 2. above are permanent enables whereas 3., 4. and 5. are
+ * temporary enables
+ *
+ * We rely on 4. to be able to access ETMCR and then use 2. above for ETM
+ * clock vote in the driver and the save-restore code uses 1. above
+ * for its vote.
+ */
+static inline void __cpu_set_etm_pwrdwn(void)
+{
+ uint32_t etm_control;
+
+ isb();
+ etm_control = etm_read(ETMCR);
+ etm_control |= ETM_CONTROL_POWERDOWN;
+ etm_write(etm_control, ETMCR);
+}
+
+static inline void __cpu_clear_etm_pwrdwn(void)
+{
+ uint32_t etm_control;
+
+ etm_control = etm_read(ETMCR);
+ etm_control &= ~ETM_CONTROL_POWERDOWN;
+ etm_write(etm_control, ETMCR);
+ isb();
+}
+
static void emit_log_char(uint8_t c)
{
int this_cpu = get_cpu();
@@ -211,21 +246,21 @@
/* enable auto-increment on reads and writes */
etb_control = AIR | AIW;
- etm_write_reg(ETB_REG_CONTROL, etb_control);
+ etb_write(etb_control, ETB_REG_CONTROL);
/* write tags to the slots before the write pointer so we can
* detect overflow */
- etm_write_reg(ETB_REG_ADDRESS, 0x00000000);
+ etb_write(0x00000000, ETB_REG_ADDRESS);
for (i = 0; i < (etm_config.etb_init_ptr >> 2); i++)
- etm_write_reg(ETB_REG_DATA, 0xDEADBEEF);
+ etb_write(0xDEADBEEF, ETB_REG_DATA);
- etm_write_reg(ETB_REG_STATUS, 0x00000000);
+ etb_write(0x00000000, ETB_REG_STATUS);
/* initialize write pointer */
- etm_write_reg(ETB_REG_ADDRESS, etm_config.etb_init_ptr);
+ etb_write(etm_config.etb_init_ptr, ETB_REG_ADDRESS);
/* multiple of 16 */
- etm_write_reg(ETB_REG_COUNT, etm_config.etb_trig_cnt & 0xFFFFFFF0);
+ etb_write(etm_config.etb_trig_cnt & 0xFFFFFFF0, ETB_REG_COUNT);
/* Enable ETB and enable the trigger counter as appropriate. A
* trigger count of 0 will be used to signify that the user wants to
@@ -236,15 +271,15 @@
etb_control |= CPTEN;
if (etm_config.etb_trig_cnt)
etb_control |= CPTM;
- etm_write_reg(ETB_REG_CONTROL, etb_control);
+ etb_write(etb_control, ETB_REG_CONTROL);
}
static void __cpu_disable_etb(void)
{
uint32_t etb_control;
- etb_control = etm_read_reg(ETB_REG_CONTROL);
+ etb_control = etb_read(ETB_REG_CONTROL);
etb_control &= ~CPTEN;
- etm_write_reg(ETB_REG_CONTROL, etb_control);
+ etb_write(etb_control, ETB_REG_CONTROL);
}
static void __cpu_enable_etm(void)
@@ -252,11 +287,11 @@
uint32_t etm_control;
unsigned long timeout = jiffies + msecs_to_jiffies(PROG_TIMEOUT_MS);
- etm_control = etm_read_reg(ETM_REG_CONTROL);
+ etm_control = etm_read(ETMCR);
etm_control &= ~ETM_CONTROL_PROGRAM;
- etm_write_reg(ETM_REG_CONTROL, etm_control);
+ etm_write(etm_control, ETMCR);
- while ((etm_read_reg(ETM_REG_STATUS) & ETM_STATUS_PROGRAMMING) == 1) {
+ while ((etm_read(ETMSR) & ETM_STATUS_PROGRAMMING) == 1) {
cpu_relax();
if (time_after(jiffies, timeout)) {
pr_err("etm: timeout while clearing prog bit\n");
@@ -270,11 +305,11 @@
uint32_t etm_control;
unsigned long timeout = jiffies + msecs_to_jiffies(PROG_TIMEOUT_MS);
- etm_control = etm_read_reg(ETM_REG_CONTROL);
+ etm_control = etm_read(ETMCR);
etm_control |= ETM_CONTROL_PROGRAM;
- etm_write_reg(ETM_REG_CONTROL, etm_control);
+ etm_write(etm_control, ETMCR);
- while ((etm_read_reg(ETM_REG_STATUS) & ETM_STATUS_PROGRAMMING) == 0) {
+ while ((etm_read(ETMSR) & ETM_STATUS_PROGRAMMING) == 0) {
cpu_relax();
if (time_after(jiffies, timeout)) {
pr_err("etm: timeout while setting prog bit\n");
@@ -291,14 +326,14 @@
get_cpu();
- etm_read_reg(0xC5); /* clear sticky bit in PDSR */
-
__cpu_disable_etb();
+ /* vote for ETM power/clock enable */
+ __cpu_clear_etm_pwrdwn();
__cpu_disable_etm();
etm_control = (etm_config.etm_00_control & ~ETM_CONTROL_POWERDOWN)
| ETM_CONTROL_PROGRAM;
- etm_write_reg(0x00, etm_control);
+ etm_write(etm_control, ETMCR);
etm_trigger = etm_config.etm_02_trigger_event;
etm_external_output = 0x406F; /* always FALSE */
@@ -314,53 +349,53 @@
etm_external_output = etm_trigger;
}
- etm_write_reg(0x02, etm_trigger);
- etm_write_reg(0x06, etm_config.etm_06_te_start_stop);
- etm_write_reg(0x07, etm_config.etm_07_te_single_addr_comp);
- etm_write_reg(0x08, etm_config.etm_08_te_event);
- etm_write_reg(0x09, etm_config.etm_09_te_control);
- etm_write_reg(0x0a, etm_config.etm_0a_fifofull_region);
- etm_write_reg(0x0b, etm_config.etm_0b_fifofull_level);
- etm_write_reg(0x0c, etm_config.etm_0c_vd_event);
- etm_write_reg(0x0d, etm_config.etm_0d_vd_single_addr_comp);
- etm_write_reg(0x0e, etm_config.etm_0e_vd_mmd);
- etm_write_reg(0x0f, etm_config.etm_0f_vd_control);
- etm_write_reg(0x10, etm_config.etm_addr_comp_value[0]);
- etm_write_reg(0x11, etm_config.etm_addr_comp_value[1]);
- etm_write_reg(0x12, etm_config.etm_addr_comp_value[2]);
- etm_write_reg(0x13, etm_config.etm_addr_comp_value[3]);
- etm_write_reg(0x14, etm_config.etm_addr_comp_value[4]);
- etm_write_reg(0x15, etm_config.etm_addr_comp_value[5]);
- etm_write_reg(0x16, etm_config.etm_addr_comp_value[6]);
- etm_write_reg(0x17, etm_config.etm_addr_comp_value[7]);
- etm_write_reg(0x20, etm_config.etm_addr_access_type[0]);
- etm_write_reg(0x21, etm_config.etm_addr_access_type[1]);
- etm_write_reg(0x22, etm_config.etm_addr_access_type[2]);
- etm_write_reg(0x23, etm_config.etm_addr_access_type[3]);
- etm_write_reg(0x24, etm_config.etm_addr_access_type[4]);
- etm_write_reg(0x25, etm_config.etm_addr_access_type[5]);
- etm_write_reg(0x26, etm_config.etm_addr_access_type[6]);
- etm_write_reg(0x27, etm_config.etm_addr_access_type[7]);
- etm_write_reg(0x30, etm_config.etm_data_comp_value[0]);
- etm_write_reg(0x32, etm_config.etm_data_comp_value[1]);
- etm_write_reg(0x40, etm_config.etm_data_comp_mask[0]);
- etm_write_reg(0x42, etm_config.etm_data_comp_mask[1]);
- etm_write_reg(0x50, etm_config.etm_counter_reload_value[0]);
- etm_write_reg(0x51, etm_config.etm_counter_reload_value[1]);
- etm_write_reg(0x54, etm_config.etm_counter_enable[0]);
- etm_write_reg(0x55, etm_config.etm_counter_enable[1]);
- etm_write_reg(0x58, etm_config.etm_counter_reload_event[0]);
- etm_write_reg(0x59, etm_config.etm_counter_reload_event[1]);
- etm_write_reg(0x60, etm_config.etm_60_seq_event_1_to_2);
- etm_write_reg(0x61, etm_config.etm_61_seq_event_2_to_1);
- etm_write_reg(0x62, etm_config.etm_62_seq_event_2_to_3);
- etm_write_reg(0x63, etm_config.etm_63_seq_event_3_to_1);
- etm_write_reg(0x64, etm_config.etm_64_seq_event_3_to_2);
- etm_write_reg(0x65, etm_config.etm_65_seq_event_1_to_3);
- etm_write_reg(0x68, etm_external_output);
- etm_write_reg(0x6c, etm_config.etm_6c_cid_comp_value_1);
- etm_write_reg(0x6f, etm_config.etm_6f_cid_comp_mask);
- etm_write_reg(0x78, etm_config.etm_78_sync_freq);
+ etm_write(etm_trigger, ETMTRIGGER);
+ etm_write(etm_config.etm_06_te_start_stop, ETMTSSCR);
+ etm_write(etm_config.etm_07_te_single_addr_comp, ETMTECR2);
+ etm_write(etm_config.etm_08_te_event, ETMTEEVR);
+ etm_write(etm_config.etm_09_te_control, ETMTECR1);
+ etm_write(etm_config.etm_0a_fifofull_region, ETMFFRR);
+ etm_write(etm_config.etm_0b_fifofull_level, ETMFFLR);
+ etm_write(etm_config.etm_0c_vd_event, ETMVDEVR);
+ etm_write(etm_config.etm_0d_vd_single_addr_comp, ETMVDCR1);
+ etm_write(etm_config.etm_0e_vd_mmd, ETMVDCR2);
+ etm_write(etm_config.etm_0f_vd_control, ETMVDCR3);
+ etm_write(etm_config.etm_addr_comp_value[0], ETMACVR0);
+ etm_write(etm_config.etm_addr_comp_value[1], ETMACVR1);
+ etm_write(etm_config.etm_addr_comp_value[2], ETMACVR2);
+ etm_write(etm_config.etm_addr_comp_value[3], ETMACVR3);
+ etm_write(etm_config.etm_addr_comp_value[4], ETMACVR4);
+ etm_write(etm_config.etm_addr_comp_value[5], ETMACVR5);
+ etm_write(etm_config.etm_addr_comp_value[6], ETMACVR6);
+ etm_write(etm_config.etm_addr_comp_value[7], ETMACVR7);
+ etm_write(etm_config.etm_addr_access_type[0], ETMACTR0);
+ etm_write(etm_config.etm_addr_access_type[1], ETMACTR1);
+ etm_write(etm_config.etm_addr_access_type[2], ETMACTR2);
+ etm_write(etm_config.etm_addr_access_type[3], ETMACTR3);
+ etm_write(etm_config.etm_addr_access_type[4], ETMACTR4);
+ etm_write(etm_config.etm_addr_access_type[5], ETMACTR5);
+ etm_write(etm_config.etm_addr_access_type[6], ETMACTR6);
+ etm_write(etm_config.etm_addr_access_type[7], ETMACTR7);
+ etm_write(etm_config.etm_data_comp_value[0], ETMDCVR0);
+ etm_write(etm_config.etm_data_comp_value[1], ETMDCVR1);
+ etm_write(etm_config.etm_data_comp_mask[0], ETMDCMR0);
+ etm_write(etm_config.etm_data_comp_mask[1], ETMDCMR1);
+ etm_write(etm_config.etm_counter_reload_value[0], ETMCNTRLDVR0);
+ etm_write(etm_config.etm_counter_reload_value[1], ETMCNTRLDVR1);
+ etm_write(etm_config.etm_counter_enable[0], ETMCNTENR0);
+ etm_write(etm_config.etm_counter_enable[1], ETMCNTENR1);
+ etm_write(etm_config.etm_counter_reload_event[0], ETMCNTRLDEVR0);
+ etm_write(etm_config.etm_counter_reload_event[1], ETMCNTRLDEVR1);
+ etm_write(etm_config.etm_60_seq_event_1_to_2, ETMSQ12EVR);
+ etm_write(etm_config.etm_61_seq_event_2_to_1, ETMSQ21EVR);
+ etm_write(etm_config.etm_62_seq_event_2_to_3, ETMSQ23EVR);
+ etm_write(etm_config.etm_63_seq_event_3_to_1, ETMSQ31EVR);
+ etm_write(etm_config.etm_64_seq_event_3_to_2, ETMSQ32EVR);
+ etm_write(etm_config.etm_65_seq_event_1_to_3, ETMSQ13EVR);
+ etm_write(etm_external_output, ETMEXTOUTEVR0);
+ etm_write(etm_config.etm_6c_cid_comp_value_1, ETMCIDCVR0);
+ etm_write(etm_config.etm_6f_cid_comp_mask, ETMCIDCMR);
+ etm_write(etm_config.etm_78_sync_freq, ETMSYNCFR);
/* Note that we must enable the ETB before we enable the ETM if we
* want to capture the "always true" trigger event. */
@@ -373,20 +408,14 @@
static void __cpu_disable_trace(void *unused)
{
- uint32_t etm_control;
-
get_cpu();
- etm_read_reg(0xC5); /* clear sticky bit in PDSR */
__cpu_disable_etm();
/* program trace enable to be low by using always false event */
- etm_write_reg(0x08, 0x6F | BIT(14));
-
- /* set the powerdown bit */
- etm_control = etm_read_reg(ETM_REG_CONTROL);
- etm_control |= ETM_CONTROL_POWERDOWN;
- etm_write_reg(ETM_REG_CONTROL, etm_control);
+ etm_write(0x6F | BIT(14), ETMTEEVR);
+ /* vote for ETM power/clock disable */
+ __cpu_set_etm_pwrdwn();
__cpu_disable_etb();
@@ -402,7 +431,8 @@
/* This register is accessible from either core.
* CPU1_extout[0] -> CPU0_extin[0]
* CPU_extout[0] -> CPU1_extin[0] */
- l2tevselr0_write(0x00000001);
+ asm volatile("mcr p15, 3, %0, c15, c5, 2" : : "r" (0x1));
+ asm volatile("isb");
}
get_cpu();
@@ -456,14 +486,14 @@
uint32_t prim_len;
uint32_t uptime = 0;
- etb_control = etm_read_reg(ETB_REG_CONTROL);
+ etb_control = etb_read(ETB_REG_CONTROL);
etb_control |= AIR;
- etm_write_reg(ETB_REG_CONTROL, etb_control);
+ etb_write(etb_control, ETB_REG_CONTROL);
- if (etm_read_reg(ETB_REG_STATUS) & OV)
+ if (etb_read(ETB_REG_STATUS) & OV)
full_slots = ETB_RAM_SLOTS;
else
- full_slots = etm_read_reg(ETB_REG_ADDRESS) >> 2;
+ full_slots = etb_read(ETB_REG_ADDRESS) >> 2;
prim_len = 28 + (full_slots * 4);
@@ -473,23 +503,24 @@
emit_log_char((prim_len >> 0) & 0xFF);
emit_log_word(uptime);
emit_log_word(ETB_DUMP_MSG_ID);
- emit_log_word(etm_read_reg(ETM_REG_CONTROL));
+ emit_log_word(etm_read(ETMCR));
emit_log_word(etm_config.etb_init_ptr >> 2);
- emit_log_word(etm_read_reg(ETB_REG_ADDRESS) >> 2);
- emit_log_word((etm_read_reg(ETB_REG_STATUS) & OV) >> 21);
+ emit_log_word(etb_read(ETB_REG_ADDRESS) >> 2);
+ emit_log_word((etb_read(ETB_REG_STATUS) & OV) >> 21);
- etm_write_reg(ETB_REG_ADDRESS, 0x00000000);
+ etb_write(0x00000000, ETB_REG_ADDRESS);
for (i = 0; i < full_slots; i++)
- emit_log_word(etm_read_reg(ETB_REG_DATA));
+ emit_log_word(etb_read(ETB_REG_DATA));
}
+/* This should match the number of ETM registers being dumped below */
+#define ETM_NUM_REGS_TO_DUMP 54
static void generate_etm_dump(void)
{
- uint32_t i;
uint32_t prim_len;
uint32_t uptime = 0;
- prim_len = 12 + (4 * ETM_NUM_REGS);
+ prim_len = 12 + (4 * ETM_NUM_REGS_TO_DUMP);
emit_log_char((DATALOG_SYNC >> 8) & 0xFF);
emit_log_char((DATALOG_SYNC >> 0) & 0xFF);
@@ -498,19 +529,65 @@
emit_log_word(uptime);
emit_log_word(ETM_DUMP_MSG_ID);
- /* do not disturb ETB_REG_ADDRESS by reading ETB_REG_DATA */
- for (i = 0; i < ETM_NUM_REGS; i++)
- if (i == ETB_REG_DATA)
- emit_log_word(0);
- else
- emit_log_word(etm_read_reg(i));
+ emit_log_word(etm_read(ETMCR));
+ emit_log_word(etm_read(ETMSR));
+ emit_log_word(etb_read(ETB_REG_CONTROL));
+ emit_log_word(etb_read(ETB_REG_STATUS));
+ emit_log_word(etb_read(ETB_REG_COUNT));
+ emit_log_word(etb_read(ETB_REG_ADDRESS));
+ emit_log_word(0); /* don't read ETB_REG_DATA, changes ETB_REG_ADDRESS */
+ emit_log_word(etm_read(ETMTRIGGER));
+ emit_log_word(etm_read(ETMTSSCR));
+ emit_log_word(etm_read(ETMTECR2));
+ emit_log_word(etm_read(ETMTEEVR));
+ emit_log_word(etm_read(ETMTECR1));
+ emit_log_word(etm_read(ETMFFRR));
+ emit_log_word(etm_read(ETMFFLR));
+ emit_log_word(etm_read(ETMVDEVR));
+ emit_log_word(etm_read(ETMVDCR1));
+ emit_log_word(etm_read(ETMVDCR2));
+ emit_log_word(etm_read(ETMVDCR3));
+ emit_log_word(etm_read(ETMACVR0));
+ emit_log_word(etm_read(ETMACVR1));
+ emit_log_word(etm_read(ETMACVR2));
+ emit_log_word(etm_read(ETMACVR3));
+ emit_log_word(etm_read(ETMACVR4));
+ emit_log_word(etm_read(ETMACVR5));
+ emit_log_word(etm_read(ETMACVR6));
+ emit_log_word(etm_read(ETMACVR7));
+ emit_log_word(etm_read(ETMACTR0));
+ emit_log_word(etm_read(ETMACTR1));
+ emit_log_word(etm_read(ETMACTR2));
+ emit_log_word(etm_read(ETMACTR3));
+ emit_log_word(etm_read(ETMACTR4));
+ emit_log_word(etm_read(ETMACTR5));
+ emit_log_word(etm_read(ETMACTR6));
+ emit_log_word(etm_read(ETMACTR7));
+ emit_log_word(etm_read(ETMDCVR0));
+ emit_log_word(etm_read(ETMDCVR1));
+ emit_log_word(etm_read(ETMDCMR0));
+ emit_log_word(etm_read(ETMDCMR1));
+ emit_log_word(etm_read(ETMCNTRLDVR0));
+ emit_log_word(etm_read(ETMCNTRLDVR1));
+ emit_log_word(etm_read(ETMCNTENR0));
+ emit_log_word(etm_read(ETMCNTENR1));
+ emit_log_word(etm_read(ETMCNTRLDEVR0));
+ emit_log_word(etm_read(ETMCNTRLDEVR1));
+ emit_log_word(etm_read(ETMSQ12EVR));
+ emit_log_word(etm_read(ETMSQ21EVR));
+ emit_log_word(etm_read(ETMSQ23EVR));
+ emit_log_word(etm_read(ETMSQ31EVR));
+ emit_log_word(etm_read(ETMSQ32EVR));
+ emit_log_word(etm_read(ETMSQ13EVR));
+ emit_log_word(etm_read(ETMEXTOUTEVR0));
+ emit_log_word(etm_read(ETMCIDCVR0));
+ emit_log_word(etm_read(ETMCIDCMR));
+ emit_log_word(etm_read(ETMSYNCFR));
}
static void dump_all(void *unused)
{
get_cpu();
- etm_read_reg(0xC5); /* clear sticky bit in PDSR in case
- * trace hasn't been enabled yet. */
__cpu_disable_etb();
generate_etm_dump();
generate_etb_dump();
@@ -900,34 +977,10 @@
.fops = &etm_dev_fops,
};
-/* etm_save_reg_check and etm_restore_reg_check should be fast
- *
- * These functions will be called either from:
- * 1. per_cpu idle thread context for idle power collapses.
- * 2. per_cpu idle thread context for hotplug/suspend power collapse for
- * nonboot cpus.
- * 3. suspend thread context for core0.
- *
- * In all cases we are guaranteed to be running on the same cpu for the
- * entire duration.
- *
- * Another assumption is that etm registers won't change after trace_enabled
- * is set. Current usage model guarantees this doesn't happen.
- *
- * Also disabling all types of power_collapses when enabling and disabling
- * trace provides mutual exclusion to be able to safely access
- * ptm.trace_enabled here.
- */
-void etm_save_reg_check(void)
+static void __cpu_clear_sticky(void *unused)
{
- if (trace_enabled)
- etm_save_reg();
-}
-
-void etm_restore_reg_check(void)
-{
- if (trace_enabled)
- etm_restore_reg();
+ etm_read(ETMPDSR); /* clear sticky bit in PDSR */
+ isb();
}
static int __init etm_init(void)
@@ -949,6 +1002,12 @@
pm_qos_add_request(&etm_qos_req, PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
+ /* No need to explicity turn on ETM clock since CP14 access go
+ * through via the autoclock turn on/off
+ */
+ __cpu_clear_sticky(NULL);
+ smp_call_function(__cpu_clear_sticky, NULL, 1);
+
cpu_to_dump = next_cpu_to_dump = 0;
pr_info("ETM/ETB intialized.\n");
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 86a2374..4f32a29 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -113,8 +113,7 @@
init_completion(&dev->cpu_killed);
return 0;
}
- etm_restore_reg_check();
- msm_restore_jtag_debug();
+ msm_jtag_restore_state();
#ifdef CONFIG_VFP
vfp_reinit();
#endif
diff --git a/arch/arm/mach-msm/idle-v7.S b/arch/arm/mach-msm/idle-v7.S
index e855357..660884c 100644
--- a/arch/arm/mach-msm/idle-v7.S
+++ b/arch/arm/mach-msm/idle-v7.S
@@ -2,7 +2,7 @@
* Idle processing for ARMv7-based Qualcomm SoCs.
*
* Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2009, 2011 Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2009, 2011-2012 Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -82,11 +82,8 @@
stmia r0!, {r1-r3}
#endif
-#ifdef CONFIG_MSM_DEBUG_ACROSS_PC
- bl msm_save_jtag_debug
-#endif
-#ifdef CONFIG_MSM_TRACE_ACROSS_PC
- bl etm_save_reg_check
+#ifdef CONFIG_MSM_JTAG
+ bl msm_jtag_save_state
#endif
ldr r0, =msm_pm_flush_l2_flag
@@ -128,11 +125,8 @@
#if defined(CONFIG_MSM_FIQ_SUPPORT)
cpsie f
#endif
-#ifdef CONFIG_MSM_TRACE_ACROSS_PC
- bl etm_restore_reg_check
-#endif
-#ifdef CONFIG_MSM_DEBUG_ACROSS_PC
- bl msm_restore_jtag_debug
+#ifdef CONFIG_MSM_JTAG
+ bl msm_jtag_restore_state
#endif
ldr r0, =saved_state /* restore registers */
#if (NR_CPUS >= 2)
@@ -225,11 +219,8 @@
#endif
stmfd sp!, {lr}
bl v7_flush_kern_cache_all
-#ifdef CONFIG_MSM_TRACE_ACROSS_PC
- bl etm_restore_reg_check
-#endif
-#ifdef CONFIG_MSM_DEBUG_ACROSS_PC
- bl msm_restore_jtag_debug
+#ifdef CONFIG_MSM_JTAG
+ bl msm_jtag_restore_state
#endif
ldmfd sp!, {lr}
mov r0, #1
diff --git a/arch/arm/mach-msm/jtag-v7.S b/arch/arm/mach-msm/jtag-v7.S
deleted file mode 100644
index 975ddf7..0000000
--- a/arch/arm/mach-msm/jtag-v7.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/*
- * JTAG support functions for ARMv7-based Qualcomm SoCs.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <linux/threads.h>
-
-#if (NR_CPUS > 2)
-#error code only tested for 1 or 2 CPUs.
-#endif
-
-/* Add 1 slot to store the register count for JTAG state */
-#define MAX_JTAG_REGS (32 + 1)
-#define MAX_DEBUG_STATE_SIZE (MAX_JTAG_REGS * 4)
-
-ENTRY(msm_save_jtag_debug)
- ldr r3, =dbg_state /* store state at dbg_state */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
- and r2, r2, #15 /* What CPU am I */
- ldr r1, =MAX_DEBUG_STATE_SIZE
- mul r2, r2, r1
- add r3, r3, r2
-#endif
-
- /* save jtag state */
- ldr r1, =0xc5ACCE55 /* set DBGOSLAR lock */
- mcr p14, 0, r1, c1, c0, 4
- isb
-
- mrc p14, 0, r1, c1, c2, 4 /* DBGOSSRR state register count */
- cmp r1, #(MAX_JTAG_REGS) /* check for state overflow */
- movgt r1, #0 /* if not enough space, don't save */
- str r1, [r3], #4 /* save count for restore */
-
-1: cmp r1, #0
- mrcne p14, 0, r2, c1, c2, 4 /* DBGOSSRR state value */
- strne r2, [r3], #4 /* push value */
- subne r1, r1, #1
- bne 1b
-
- mcr p14, 0, r1, c1, c0, 4 /* unlock DBGOSLAR */
- isb
-
- bx lr
-
-ENTRY(msm_restore_jtag_debug)
- /* restore debug registers after power collapse */
- ldr r3, =dbg_state /* load state from dbg_state */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
- and r2, r2, #15 /* What CPU am I */
- ldr r1, =MAX_DEBUG_STATE_SIZE
- mul r2, r2, r1
- add r3, r3, r2
-#endif
-
- /* restore jtag state */
- mrc p14, 0, r1, c1, c5, 4 /* clear sticky power down bit */
- isb
- ldr r1, =0xc5ACCE55 /* set DBGOSLAR lock */
- mcr p14, 0, r1, c1, c0, 4
- isb
-
- mrc p14, 0, r1, c1, c2, 4 /* DBGOSSRR dummy read (required)*/
- ldr r1, [r3], #4 /* load saved count */
- cmp r1, #0 /* skip if none stored */
- beq msm_pm_dbg_restore_end
-
- /* restores debug state except DBGDSCR */
-1: ldr r2, [r3], #4
- cmp r1, #0x10 /* DBGDSCR special case */
- biceq r2, r2, #0xc000 /* DBGDSCR = DBGDSCR & ~0xc000 */
- mcr p14, 0, r2, c1, c2, 4 /* DBGOSSRR write state value */
- subs r1, r1, #1
- bne 1b
-
- ldr r3, =dbg_state /* load state from dbg_state */
-#if (NR_CPUS >= 2)
- mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
- and r2, r2, #15 /* What CPU am I */
- ldr r1, =MAX_DEBUG_STATE_SIZE
- mul r2, r2, r1
- add r3, r3, r2
-#endif
- ldr r1, =0xc5ACCE55 /* set DBGOSLAR lock */
- mcr p14, 0, r1, c1, c0, 4
- isb
-
- mrc p14, 0, r1, c1, c2, 4 /* DBGOSSRR dummy read (required)*/
- ldr r1, [r3], #4 /* load saved count */
- cmp r1, #0 /* skip if none stored */
- beq msm_pm_dbg_restore_end
-
- /* second pass to restore debug state including DBGDSCR */
-1: ldr r2, [r3], #4
- mcr p14, 0, r2, c1, c2, 4 /* DBGOSSRR write state value */
- subs r1,r1,#1
- bne 1b
-msm_pm_dbg_restore_end:
- mcr p14, 0, r1, c1, c0, 4 /* unlock DBGOSLAR */
- isb
-
- bx lr
-
-
- .data
-
-dbg_state:
- .space MAX_DEBUG_STATE_SIZE * NR_CPUS
diff --git a/arch/arm/mach-msm/jtag.c b/arch/arm/mach-msm/jtag.c
new file mode 100644
index 0000000..f720fa9
--- /dev/null
+++ b/arch/arm/mach-msm/jtag.c
@@ -0,0 +1,1108 @@
+/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <linux/printk.h>
+#include <linux/ratelimit.h>
+
+#include "qdss.h"
+#include "cp14.h"
+
+#define MAX_DBG_REGS (90)
+#define MAX_DBG_STATE_SIZE (MAX_DBG_REGS * num_possible_cpus())
+#define MAX_ETM_REGS (78)
+#define MAX_ETM_STATE_SIZE (MAX_ETM_REGS * num_possible_cpus())
+
+#define DBGDSCR_MASK (0x6C30FC3C)
+#define CPMR_ETMCLKEN (0x8)
+
+
+struct dbg_ctx {
+ uint8_t arch;
+ bool arch_supported;
+ uint8_t nr_wp;
+ uint8_t nr_bp;
+ uint8_t nr_ctx_cmp;
+ uint32_t *state;
+};
+static struct dbg_ctx dbg;
+
+struct etm_ctx {
+ uint8_t arch;
+ bool arch_supported;
+ uint8_t nr_addr_cmp;
+ uint8_t nr_cntr;
+ uint8_t nr_ext_inp;
+ uint8_t nr_ext_out;
+ uint8_t nr_ctxid_cmp;
+ uint32_t *state;
+};
+static struct etm_ctx etm;
+
+static int dbg_read_bxr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ state[i++] = dbg_read(DBGBVR0);
+ state[i++] = dbg_read(DBGBCR0);
+ break;
+ case 1:
+ state[i++] = dbg_read(DBGBVR1);
+ state[i++] = dbg_read(DBGBCR1);
+ break;
+ case 2:
+ state[i++] = dbg_read(DBGBVR2);
+ state[i++] = dbg_read(DBGBCR2);
+ break;
+ case 3:
+ state[i++] = dbg_read(DBGBVR3);
+ state[i++] = dbg_read(DBGBVR3);
+ break;
+ case 4:
+ state[i++] = dbg_read(DBGBVR4);
+ state[i++] = dbg_read(DBGBCR4);
+ break;
+ case 5:
+ state[i++] = dbg_read(DBGBVR5);
+ state[i++] = dbg_read(DBGBVR5);
+ break;
+ case 6:
+ state[i++] = dbg_read(DBGBVR6);
+ state[i++] = dbg_read(DBGBCR6);
+ break;
+ case 7:
+ state[i++] = dbg_read(DBGBVR7);
+ state[i++] = dbg_read(DBGBCR7);
+ break;
+ case 8:
+ state[i++] = dbg_read(DBGBVR8);
+ state[i++] = dbg_read(DBGBCR8);
+ break;
+ case 9:
+ state[i++] = dbg_read(DBGBVR9);
+ state[i++] = dbg_read(DBGBCR9);
+ break;
+ case 10:
+ state[i++] = dbg_read(DBGBVR10);
+ state[i++] = dbg_read(DBGBCR10);
+ break;
+ case 11:
+ state[i++] = dbg_read(DBGBVR11);
+ state[i++] = dbg_read(DBGBCR11);
+ break;
+ case 12:
+ state[i++] = dbg_read(DBGBVR12);
+ state[i++] = dbg_read(DBGBCR12);
+ break;
+ case 13:
+ state[i++] = dbg_read(DBGBVR13);
+ state[i++] = dbg_read(DBGBCR13);
+ break;
+ case 14:
+ state[i++] = dbg_read(DBGBVR14);
+ state[i++] = dbg_read(DBGBCR14);
+ break;
+ case 15:
+ state[i++] = dbg_read(DBGBVR15);
+ state[i++] = dbg_read(DBGBCR15);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int dbg_write_bxr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ dbg_write(state[i++], DBGBVR0);
+ dbg_write(state[i++], DBGBCR0);
+ break;
+ case 1:
+ dbg_write(state[i++], DBGBVR1);
+ dbg_write(state[i++], DBGBCR1);
+ break;
+ case 2:
+ dbg_write(state[i++], DBGBVR2);
+ dbg_write(state[i++], DBGBCR2);
+ break;
+ case 3:
+ dbg_write(state[i++], DBGBVR3);
+ dbg_write(state[i++], DBGBVR3);
+ break;
+ case 4:
+ dbg_write(state[i++], DBGBVR4);
+ dbg_write(state[i++], DBGBCR4);
+ break;
+ case 5:
+ dbg_write(state[i++], DBGBVR5);
+ dbg_write(state[i++], DBGBVR5);
+ break;
+ case 6:
+ dbg_write(state[i++], DBGBVR6);
+ dbg_write(state[i++], DBGBCR6);
+ break;
+ case 7:
+ dbg_write(state[i++], DBGBVR7);
+ dbg_write(state[i++], DBGBCR7);
+ break;
+ case 8:
+ dbg_write(state[i++], DBGBVR8);
+ dbg_write(state[i++], DBGBCR8);
+ break;
+ case 9:
+ dbg_write(state[i++], DBGBVR9);
+ dbg_write(state[i++], DBGBCR9);
+ break;
+ case 10:
+ dbg_write(state[i++], DBGBVR10);
+ dbg_write(state[i++], DBGBCR10);
+ break;
+ case 11:
+ dbg_write(state[i++], DBGBVR11);
+ dbg_write(state[i++], DBGBCR11);
+ break;
+ case 12:
+ dbg_write(state[i++], DBGBVR12);
+ dbg_write(state[i++], DBGBCR12);
+ break;
+ case 13:
+ dbg_write(state[i++], DBGBVR13);
+ dbg_write(state[i++], DBGBCR13);
+ break;
+ case 14:
+ dbg_write(state[i++], DBGBVR14);
+ dbg_write(state[i++], DBGBCR14);
+ break;
+ case 15:
+ dbg_write(state[i++], DBGBVR15);
+ dbg_write(state[i++], DBGBCR15);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int dbg_read_wxr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ state[i++] = dbg_read(DBGWVR0);
+ state[i++] = dbg_read(DBGWCR0);
+ break;
+ case 1:
+ state[i++] = dbg_read(DBGWVR1);
+ state[i++] = dbg_read(DBGWCR1);
+ break;
+ case 2:
+ state[i++] = dbg_read(DBGWVR2);
+ state[i++] = dbg_read(DBGWCR2);
+ break;
+ case 3:
+ state[i++] = dbg_read(DBGWVR3);
+ state[i++] = dbg_read(DBGWCR3);
+ break;
+ case 4:
+ state[i++] = dbg_read(DBGWVR4);
+ state[i++] = dbg_read(DBGWCR4);
+ break;
+ case 5:
+ state[i++] = dbg_read(DBGWVR5);
+ state[i++] = dbg_read(DBGWCR5);
+ break;
+ case 6:
+ state[i++] = dbg_read(DBGWVR6);
+ state[i++] = dbg_read(DBGWCR6);
+ break;
+ case 7:
+ state[i++] = dbg_read(DBGWVR7);
+ state[i++] = dbg_read(DBGWCR7);
+ break;
+ case 8:
+ state[i++] = dbg_read(DBGWVR8);
+ state[i++] = dbg_read(DBGWCR8);
+ break;
+ case 9:
+ state[i++] = dbg_read(DBGWVR9);
+ state[i++] = dbg_read(DBGWCR9);
+ break;
+ case 10:
+ state[i++] = dbg_read(DBGWVR10);
+ state[i++] = dbg_read(DBGWCR10);
+ break;
+ case 11:
+ state[i++] = dbg_read(DBGWVR11);
+ state[i++] = dbg_read(DBGWCR11);
+ break;
+ case 12:
+ state[i++] = dbg_read(DBGWVR12);
+ state[i++] = dbg_read(DBGWCR12);
+ break;
+ case 13:
+ state[i++] = dbg_read(DBGWVR13);
+ state[i++] = dbg_read(DBGWCR13);
+ break;
+ case 14:
+ state[i++] = dbg_read(DBGWVR14);
+ state[i++] = dbg_read(DBGWCR14);
+ break;
+ case 15:
+ state[i++] = dbg_read(DBGWVR15);
+ state[i++] = dbg_read(DBGWCR15);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int dbg_write_wxr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ dbg_write(state[i++], DBGWVR0);
+ dbg_write(state[i++], DBGWCR0);
+ break;
+ case 1:
+ dbg_write(state[i++], DBGWVR1);
+ dbg_write(state[i++], DBGWCR1);
+ break;
+ case 2:
+ dbg_write(state[i++], DBGWVR2);
+ dbg_write(state[i++], DBGWCR2);
+ break;
+ case 3:
+ dbg_write(state[i++], DBGWVR3);
+ dbg_write(state[i++], DBGWCR3);
+ break;
+ case 4:
+ dbg_write(state[i++], DBGWVR4);
+ dbg_write(state[i++], DBGWCR4);
+ break;
+ case 5:
+ dbg_write(state[i++], DBGWVR5);
+ dbg_write(state[i++], DBGWCR5);
+ break;
+ case 6:
+ dbg_write(state[i++], DBGWVR6);
+ dbg_write(state[i++], DBGWCR6);
+ break;
+ case 7:
+ dbg_write(state[i++], DBGWVR7);
+ dbg_write(state[i++], DBGWCR7);
+ break;
+ case 8:
+ dbg_write(state[i++], DBGWVR8);
+ dbg_write(state[i++], DBGWCR8);
+ break;
+ case 9:
+ dbg_write(state[i++], DBGWVR9);
+ dbg_write(state[i++], DBGWCR9);
+ break;
+ case 10:
+ dbg_write(state[i++], DBGWVR10);
+ dbg_write(state[i++], DBGWCR10);
+ break;
+ case 11:
+ dbg_write(state[i++], DBGWVR11);
+ dbg_write(state[i++], DBGWCR11);
+ break;
+ case 12:
+ dbg_write(state[i++], DBGWVR12);
+ dbg_write(state[i++], DBGWCR12);
+ break;
+ case 13:
+ dbg_write(state[i++], DBGWVR13);
+ dbg_write(state[i++], DBGWCR13);
+ break;
+ case 14:
+ dbg_write(state[i++], DBGWVR14);
+ dbg_write(state[i++], DBGWCR14);
+ break;
+ case 15:
+ dbg_write(state[i++], DBGWVR15);
+ dbg_write(state[i++], DBGWCR15);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static inline bool dbg_arch_supported(uint8_t arch)
+{
+ switch (arch) {
+ case ARM_DEBUG_ARCH_V7_1:
+ case ARM_DEBUG_ARCH_V7:
+ case ARM_DEBUG_ARCH_V7B:
+ break;
+ default:
+ return false;
+ }
+ return true;
+}
+
+
+static inline void dbg_save_state(int cpu)
+{
+ int i, j, cnt;
+
+ i = cpu * MAX_DBG_REGS;
+
+ switch (dbg.arch) {
+ case ARM_DEBUG_ARCH_V7_1:
+ /* Set OS lock to inform the debugger that the OS is in the
+ * process of saving debug registers. It prevents accidental
+ * modification of the debug regs by the external debugger.
+ */
+ dbg_write(OSLOCK_MAGIC, DBGOSLAR);
+ isb();
+
+ /* We skip saving DBGBXVRn since not supported on Krait */
+
+ dbg.state[i++] = dbg_read(DBGWFAR);
+ for (j = 0; j < dbg.nr_bp; j++)
+ i = dbg_read_bxr(dbg.state, i, j);
+ for (j = 0; j < dbg.nr_wp; j++)
+ i = dbg_read_wxr(dbg.state, i, j);
+ dbg.state[i++] = dbg_read(DBGVCR);
+ dbg.state[i++] = dbg_read(DBGCLAIMCLR);
+ dbg.state[i++] = dbg_read(DBGDTRTXext);
+ dbg.state[i++] = dbg_read(DBGDTRRXext);
+ dbg.state[i++] = dbg_read(DBGDSCRext);
+
+ /* Set the OS double lock */
+ isb();
+ dbg_write(0x1, DBGOSDLR);
+ isb();
+ break;
+ case ARM_DEBUG_ARCH_V7B:
+ case ARM_DEBUG_ARCH_V7:
+ /* Set OS lock to inform the debugger that the OS is in the
+ * process of saving dbg registers. It prevents accidental
+ * modification of the dbg regs by the external debugger
+ * and resets the internal counter.
+ */
+ dbg_write(OSLOCK_MAGIC, DBGOSLAR);
+ isb();
+
+ cnt = dbg_read(DBGOSSRR); /* save count for restore */
+ /* MAX_DBG_REGS = no of dbg regs + 1 (for storing the reg count)
+ * check for state overflow, if not enough space, don't save
+ */
+ if (cnt >= MAX_DBG_REGS)
+ cnt = 0;
+ dbg.state[i++] = cnt;
+ for (j = 0; j < cnt; j++)
+ dbg.state[i++] = dbg_read(DBGOSSRR);
+ break;
+ default:
+ pr_err_ratelimited("unsupported dbg arch %d in %s\n", dbg.arch,
+ __func__);
+ }
+}
+
+static inline void dbg_restore_state(int cpu)
+{
+ int i, j, cnt;
+
+ i = cpu * MAX_DBG_REGS;
+
+ switch (dbg.arch) {
+ case ARM_DEBUG_ARCH_V7_1:
+ /* Clear the OS double lock */
+ isb();
+ dbg_write(0x0, DBGOSDLR);
+ isb();
+
+ /* Set OS lock. Lock will already be set after power collapse
+ * but this write is included to ensure it is set.
+ */
+ dbg_write(OSLOCK_MAGIC, DBGOSLAR);
+ isb();
+
+ /* We skip restoring DBGBXVRn since not supported on Krait */
+
+ dbg_write(dbg.state[i++], DBGWFAR);
+ for (j = 0; j < dbg.nr_bp; j++)
+ i = dbg_write_bxr(dbg.state, i, j);
+ for (j = 0; j < dbg.nr_wp; j++)
+ i = dbg_write_wxr(dbg.state, i, j);
+ dbg_write(dbg.state[i++], DBGVCR);
+ dbg_write(dbg.state[i++], DBGCLAIMSET);
+ dbg_write(dbg.state[i++], DBGDTRTXext);
+ dbg_write(dbg.state[i++], DBGDTRRXext);
+ dbg_write(dbg.state[i++] & DBGDSCR_MASK, DBGDSCRext);
+
+ isb();
+ dbg_write(0x0, DBGOSLAR);
+ isb();
+ break;
+ case ARM_DEBUG_ARCH_V7B:
+ case ARM_DEBUG_ARCH_V7:
+ /* Clear sticky bit */
+ dbg_read(DBGPRSR);
+ isb();
+
+ /* Set OS lock. Lock will already be set after power collapse
+ * but this write is required to reset the internal counter used
+ * for DBG state restore.
+ */
+ dbg_write(OSLOCK_MAGIC, DBGOSLAR);
+ isb();
+
+ dbg_read(DBGOSSRR); /* dummy read of OSSRR */
+ cnt = dbg.state[i++];
+ for (j = 0; j < cnt; j++) {
+ /* DBGDSCR special case
+ * DBGDSCR = DBGDSCR & DBGDSCR_MASK
+ */
+ if (j == 20)
+ dbg_write(dbg.state[i++] & DBGDSCR_MASK,
+ DBGOSSRR);
+ else
+ dbg_write(dbg.state[i++], DBGOSSRR);
+ }
+
+ /* Clear the OS lock */
+ isb();
+ dbg_write(0x0, DBGOSLAR);
+ isb();
+ break;
+ default:
+ pr_err_ratelimited("unsupported dbg arch %d in %s\n", dbg.arch,
+ __func__);
+ }
+
+}
+
+static int etm_read_acxr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ state[i++] = etm_read(ETMACVR0);
+ state[i++] = etm_read(ETMACTR0);
+ break;
+ case 1:
+ state[i++] = etm_read(ETMACVR1);
+ state[i++] = etm_read(ETMACTR1);
+ break;
+ case 2:
+ state[i++] = etm_read(ETMACVR2);
+ state[i++] = etm_read(ETMACTR2);
+ break;
+ case 3:
+ state[i++] = etm_read(ETMACVR3);
+ state[i++] = etm_read(ETMACTR3);
+ break;
+ case 4:
+ state[i++] = etm_read(ETMACVR4);
+ state[i++] = etm_read(ETMACTR4);
+ break;
+ case 5:
+ state[i++] = etm_read(ETMACVR5);
+ state[i++] = etm_read(ETMACTR5);
+ break;
+ case 6:
+ state[i++] = etm_read(ETMACVR6);
+ state[i++] = etm_read(ETMACTR6);
+ break;
+ case 7:
+ state[i++] = etm_read(ETMACVR7);
+ state[i++] = etm_read(ETMACTR7);
+ break;
+ case 8:
+ state[i++] = etm_read(ETMACVR8);
+ state[i++] = etm_read(ETMACTR8);
+ break;
+ case 9:
+ state[i++] = etm_read(ETMACVR9);
+ state[i++] = etm_read(ETMACTR9);
+ break;
+ case 10:
+ state[i++] = etm_read(ETMACVR10);
+ state[i++] = etm_read(ETMACTR10);
+ break;
+ case 11:
+ state[i++] = etm_read(ETMACVR11);
+ state[i++] = etm_read(ETMACTR11);
+ break;
+ case 12:
+ state[i++] = etm_read(ETMACVR12);
+ state[i++] = etm_read(ETMACTR12);
+ break;
+ case 13:
+ state[i++] = etm_read(ETMACVR13);
+ state[i++] = etm_read(ETMACTR13);
+ break;
+ case 14:
+ state[i++] = etm_read(ETMACVR14);
+ state[i++] = etm_read(ETMACTR14);
+ break;
+ case 15:
+ state[i++] = etm_read(ETMACVR15);
+ state[i++] = etm_read(ETMACTR15);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_write_acxr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ etm_write(state[i++], ETMACVR0);
+ etm_write(state[i++], ETMACTR0);
+ break;
+ case 1:
+ etm_write(state[i++], ETMACVR1);
+ etm_write(state[i++], ETMACTR1);
+ break;
+ case 2:
+ etm_write(state[i++], ETMACVR2);
+ etm_write(state[i++], ETMACTR2);
+ break;
+ case 3:
+ etm_write(state[i++], ETMACVR3);
+ etm_write(state[i++], ETMACTR3);
+ break;
+ case 4:
+ etm_write(state[i++], ETMACVR4);
+ etm_write(state[i++], ETMACTR4);
+ break;
+ case 5:
+ etm_write(state[i++], ETMACVR5);
+ etm_write(state[i++], ETMACTR5);
+ break;
+ case 6:
+ etm_write(state[i++], ETMACVR6);
+ etm_write(state[i++], ETMACTR6);
+ break;
+ case 7:
+ etm_write(state[i++], ETMACVR7);
+ etm_write(state[i++], ETMACTR7);
+ break;
+ case 8:
+ etm_write(state[i++], ETMACVR8);
+ etm_write(state[i++], ETMACTR8);
+ break;
+ case 9:
+ etm_write(state[i++], ETMACVR9);
+ etm_write(state[i++], ETMACTR9);
+ break;
+ case 10:
+ etm_write(state[i++], ETMACVR10);
+ etm_write(state[i++], ETMACTR10);
+ break;
+ case 11:
+ etm_write(state[i++], ETMACVR11);
+ etm_write(state[i++], ETMACTR11);
+ break;
+ case 12:
+ etm_write(state[i++], ETMACVR12);
+ etm_write(state[i++], ETMACTR12);
+ break;
+ case 13:
+ etm_write(state[i++], ETMACVR13);
+ etm_write(state[i++], ETMACTR13);
+ break;
+ case 14:
+ etm_write(state[i++], ETMACVR14);
+ etm_write(state[i++], ETMACTR14);
+ break;
+ case 15:
+ etm_write(state[i++], ETMACVR15);
+ etm_write(state[i++], ETMACTR15);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_read_cntx(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ state[i++] = etm_read(ETMCNTRLDVR0);
+ state[i++] = etm_read(ETMCNTENR0);
+ state[i++] = etm_read(ETMCNTRLDEVR0);
+ state[i++] = etm_read(ETMCNTVR0);
+ break;
+ case 1:
+ state[i++] = etm_read(ETMCNTRLDVR1);
+ state[i++] = etm_read(ETMCNTENR1);
+ state[i++] = etm_read(ETMCNTRLDEVR1);
+ state[i++] = etm_read(ETMCNTVR1);
+ break;
+ case 2:
+ state[i++] = etm_read(ETMCNTRLDVR2);
+ state[i++] = etm_read(ETMCNTENR2);
+ state[i++] = etm_read(ETMCNTRLDEVR2);
+ state[i++] = etm_read(ETMCNTVR2);
+ break;
+ case 3:
+ state[i++] = etm_read(ETMCNTRLDVR3);
+ state[i++] = etm_read(ETMCNTENR3);
+ state[i++] = etm_read(ETMCNTRLDEVR3);
+ state[i++] = etm_read(ETMCNTVR3);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_write_cntx(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ etm_write(state[i++], ETMCNTRLDVR0);
+ etm_write(state[i++], ETMCNTENR0);
+ etm_write(state[i++], ETMCNTRLDEVR0);
+ etm_write(state[i++], ETMCNTVR0);
+ break;
+ case 1:
+ etm_write(state[i++], ETMCNTRLDVR1);
+ etm_write(state[i++], ETMCNTENR1);
+ etm_write(state[i++], ETMCNTRLDEVR1);
+ etm_write(state[i++], ETMCNTVR1);
+ break;
+ case 2:
+ etm_write(state[i++], ETMCNTRLDVR2);
+ etm_write(state[i++], ETMCNTENR2);
+ etm_write(state[i++], ETMCNTRLDEVR2);
+ etm_write(state[i++], ETMCNTVR2);
+ break;
+ case 3:
+ etm_write(state[i++], ETMCNTRLDVR3);
+ etm_write(state[i++], ETMCNTENR3);
+ etm_write(state[i++], ETMCNTRLDEVR3);
+ etm_write(state[i++], ETMCNTVR3);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_read_extoutevr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ state[i++] = etm_read(ETMEXTOUTEVR0);
+ break;
+ case 1:
+ state[i++] = etm_read(ETMEXTOUTEVR1);
+ break;
+ case 2:
+ state[i++] = etm_read(ETMEXTOUTEVR2);
+ break;
+ case 3:
+ state[i++] = etm_read(ETMEXTOUTEVR3);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_write_extoutevr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ etm_write(state[i++], ETMEXTOUTEVR0);
+ break;
+ case 1:
+ etm_write(state[i++], ETMEXTOUTEVR1);
+ break;
+ case 2:
+ etm_write(state[i++], ETMEXTOUTEVR2);
+ break;
+ case 3:
+ etm_write(state[i++], ETMEXTOUTEVR3);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_read_cidcvr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ state[i++] = etm_read(ETMCIDCVR0);
+ break;
+ case 1:
+ state[i++] = etm_read(ETMCIDCVR1);
+ break;
+ case 2:
+ state[i++] = etm_read(ETMCIDCVR2);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static int etm_write_cidcvr(uint32_t *state, int i, int j)
+{
+ switch (j) {
+ case 0:
+ etm_write(state[i++], ETMCIDCVR0);
+ break;
+ case 1:
+ etm_write(state[i++], ETMCIDCVR1);
+ break;
+ case 2:
+ etm_write(state[i++], ETMCIDCVR2);
+ break;
+ default:
+ pr_err_ratelimited("idx %d out of bounds in %s\n", j, __func__);
+ }
+ return i;
+}
+
+static inline void etm_clk_disable(void)
+{
+ uint32_t cpmr;
+
+ isb();
+ asm volatile("mrc p15, 7, %0, c15, c0, 5" : "=r" (cpmr));
+ cpmr &= ~CPMR_ETMCLKEN;
+ asm volatile("mcr p15, 7, %0, c15, c0, 5" : : "r" (cpmr));
+}
+
+static inline void etm_clk_enable(void)
+{
+ uint32_t cpmr;
+
+ asm volatile("mrc p15, 7, %0, c15, c0, 5" : "=r" (cpmr));
+ cpmr |= CPMR_ETMCLKEN;
+ asm volatile("mcr p15, 7, %0, c15, c0, 5" : : "r" (cpmr));
+ isb();
+}
+
+static inline bool etm_arch_supported(uint8_t arch)
+{
+ switch (arch) {
+ case ETM_ARCH_V3_3:
+ case PFT_ARCH_V1_1:
+ break;
+ default:
+ return false;
+ }
+ return true;
+}
+
+static inline void etm_save_state(int cpu)
+{
+ int i, j, cnt;
+
+ i = cpu * MAX_ETM_REGS;
+
+ /* Vote for ETM power/clock enable */
+ etm_clk_enable();
+
+ switch (etm.arch) {
+ case PFT_ARCH_V1_1:
+ /* Set OS lock to inform the debugger that the OS is in the
+ * process of saving etm registers. It prevents accidental
+ * modification of the etm regs by the external debugger.
+ *
+ * We don't poll for ETMSR[1] since it doesn't get set
+ */
+ etm_write(OSLOCK_MAGIC, ETMOSLAR);
+ isb();
+
+ etm.state[i++] = etm_read(ETMCR);
+ etm.state[i++] = etm_read(ETMTRIGGER);
+ etm.state[i++] = etm_read(ETMSR);
+ etm.state[i++] = etm_read(ETMTSSCR);
+ etm.state[i++] = etm_read(ETMTEEVR);
+ etm.state[i++] = etm_read(ETMTECR1);
+ etm.state[i++] = etm_read(ETMFFLR);
+ for (j = 0; j < etm.nr_addr_cmp; j++)
+ i = etm_read_acxr(etm.state, i, j);
+ for (j = 0; j < etm.nr_cntr; j++)
+ i = etm_read_cntx(etm.state, i, j);
+ etm.state[i++] = etm_read(ETMSQ12EVR);
+ etm.state[i++] = etm_read(ETMSQ21EVR);
+ etm.state[i++] = etm_read(ETMSQ23EVR);
+ etm.state[i++] = etm_read(ETMSQ31EVR);
+ etm.state[i++] = etm_read(ETMSQ32EVR);
+ etm.state[i++] = etm_read(ETMSQ13EVR);
+ etm.state[i++] = etm_read(ETMSQR);
+ for (j = 0; j < etm.nr_ext_out; j++)
+ i = etm_read_extoutevr(etm.state, i, j);
+ for (j = 0; j < etm.nr_ctxid_cmp; j++)
+ i = etm_read_cidcvr(etm.state, i, j);
+ etm.state[i++] = etm_read(ETMCIDCMR);
+ etm.state[i++] = etm_read(ETMSYNCFR);
+ etm.state[i++] = etm_read(ETMEXTINSELR);
+ etm.state[i++] = etm_read(ETMTSEVR);
+ etm.state[i++] = etm_read(ETMAUXCR);
+ etm.state[i++] = etm_read(ETMTRACEIDR);
+ etm.state[i++] = etm_read(ETMVMIDCVR);
+ etm.state[i++] = etm_read(ETMCLAIMCLR);
+ break;
+ case ETM_ARCH_V3_3:
+ /* In ETMv3.3, it is possible for the coresight lock to be
+ * implemented for CP14 interface but we currently assume that
+ * it is not, so no need to unlock and lock coresight lock
+ * (ETMLAR).
+ *
+ * Also since save and restore is not conditional i.e. always
+ * occurs when enabled, there is no need to clear the sticky
+ * PDSR bit while saving. It will be cleared during boot up/init
+ * and then by the restore procedure.
+ */
+
+ /* Set OS lock to inform the debugger that the OS is in the
+ * process of saving etm registers. It prevents accidental
+ * modification of the etm regs by the external debugger
+ * and resets the internal counter.
+ */
+ etm_write(OSLOCK_MAGIC, ETMOSLAR);
+ isb();
+
+ cnt = etm_read(ETMOSSRR); /* save count for restore */
+ /* MAX_ETM_REGS = no of etm regs + 1 (for storing the reg count)
+ * check for state overflow, if not enough space, don't save
+ */
+ if (cnt >= MAX_ETM_REGS)
+ cnt = 0;
+ etm.state[i++] = cnt;
+ for (j = 0; j < cnt; j++)
+ etm.state[i++] = etm_read(ETMOSSRR);
+ break;
+ default:
+ pr_err_ratelimited("unsupported etm arch %d in %s\n", etm.arch,
+ __func__);
+ }
+
+ /* Vote for ETM power/clock disable */
+ etm_clk_disable();
+}
+
+static inline void etm_restore_state(int cpu)
+{
+ int i, j, cnt;
+
+ i = cpu * MAX_ETM_REGS;
+
+ /* Vote for ETM power/clock enable */
+ etm_clk_enable();
+
+ switch (etm.arch) {
+ case PFT_ARCH_V1_1:
+ /* Set OS lock. Lock will already be set after power collapse
+ * but this write is included to ensure it is set.
+ *
+ * We don't poll for ETMSR[1] since it doesn't get set
+ */
+ etm_write(OSLOCK_MAGIC, ETMOSLAR);
+ isb();
+
+ etm_write(etm.state[i++], ETMCR);
+ etm_write(etm.state[i++], ETMTRIGGER);
+ etm_write(etm.state[i++], ETMSR);
+ etm_write(etm.state[i++], ETMTSSCR);
+ etm_write(etm.state[i++], ETMTEEVR);
+ etm_write(etm.state[i++], ETMTECR1);
+ etm_write(etm.state[i++], ETMFFLR);
+ for (j = 0; j < etm.nr_addr_cmp; j++)
+ i = etm_write_acxr(etm.state, i, j);
+ for (j = 0; j < etm.nr_cntr; j++)
+ i = etm_write_cntx(etm.state, i, j);
+ etm_write(etm.state[i++], ETMSQ12EVR);
+ etm_write(etm.state[i++], ETMSQ21EVR);
+ etm_write(etm.state[i++], ETMSQ23EVR);
+ etm_write(etm.state[i++], ETMSQ32EVR);
+ etm_write(etm.state[i++], ETMSQ13EVR);
+ etm_write(etm.state[i++], ETMSQ31EVR);
+ etm_write(etm.state[i++], ETMSQR);
+ for (j = 0; j < etm.nr_ext_out; j++)
+ i = etm_write_extoutevr(etm.state, i, j);
+ for (j = 0; j < etm.nr_ctxid_cmp; j++)
+ i = etm_write_cidcvr(etm.state, i, j);
+ etm_write(etm.state[i++], ETMCIDCMR);
+ etm_write(etm.state[i++], ETMSYNCFR);
+ etm_write(etm.state[i++], ETMEXTINSELR);
+ etm_write(etm.state[i++], ETMTSEVR);
+ etm_write(etm.state[i++], ETMAUXCR);
+ etm_write(etm.state[i++], ETMTRACEIDR);
+ etm_write(etm.state[i++], ETMVMIDCVR);
+ etm_write(etm.state[i++], ETMCLAIMSET);
+
+ /* Clear the OS lock */
+ isb();
+ etm_write(0x0, ETMOSLAR);
+ isb();
+ break;
+ case ETM_ARCH_V3_3:
+ /* In ETMv3.3, it is possible for the coresight lock to be
+ * implemented for CP14 interface but we currently assume that
+ * it is not, so no need to unlock and lock coresight lock
+ * (ETMLAR).
+ */
+
+ /* Clear sticky bit */
+ etm_read(ETMPDSR);
+ isb();
+
+ /* Set OS lock. Lock will already be set after power collapse
+ * but this write is required to reset the internal counter used
+ * for ETM state restore.
+ */
+ etm_write(OSLOCK_MAGIC, ETMOSLAR);
+ isb();
+
+ etm_read(ETMOSSRR); /* dummy read of OSSRR */
+ cnt = etm.state[i++];
+ for (j = 0; j < cnt; j++)
+ etm_write(etm.state[i++], ETMOSSRR);
+
+ /* Clear the OS lock */
+ isb();
+ etm_write(0x0, ETMOSLAR);
+ isb();
+ break;
+ default:
+ pr_err_ratelimited("unsupported etm arch %d in %s\n", etm.arch,
+ __func__);
+ }
+
+ /* Vote for ETM power/clock disable */
+ etm_clk_disable();
+}
+
+/* msm_jtag_save_state and msm_jtag_restore_state should be fast
+ *
+ * These functions will be called either from:
+ * 1. per_cpu idle thread context for idle power collapses.
+ * 2. per_cpu idle thread context for hotplug/suspend power collapse for
+ * nonboot cpus.
+ * 3. suspend thread context for core0.
+ *
+ * In all cases we are guaranteed to be running on the same cpu for the
+ * entire duration.
+ */
+void msm_jtag_save_state(void)
+{
+ int cpu;
+
+ cpu = raw_smp_processor_id();
+
+ if (dbg.arch_supported)
+ dbg_save_state(cpu);
+ if (etm.arch_supported)
+ etm_save_state(cpu);
+}
+
+void msm_jtag_restore_state(void)
+{
+ int cpu;
+
+ cpu = raw_smp_processor_id();
+
+ if (dbg.arch_supported)
+ dbg_restore_state(cpu);
+ if (etm.arch_supported)
+ etm_restore_state(cpu);
+}
+
+static int __init msm_jtag_dbg_init(void)
+{
+ int ret;
+ uint32_t dbgdidr;
+
+ /* This will run on core0 so use it to populate parameters */
+
+ /* Populate dbg_ctx data */
+ dbgdidr = dbg_read(DBGDIDR);
+ dbg.arch = BMVAL(dbgdidr, 16, 19);
+ dbg.arch_supported = dbg_arch_supported(dbg.arch);
+ if (!dbg.arch_supported) {
+ pr_info("dbg arch %u not supported\n", dbg.arch);
+ goto dbg_out;
+ }
+ dbg.nr_ctx_cmp = BMVAL(dbgdidr, 20, 23);
+ dbg.nr_bp = BMVAL(dbgdidr, 24, 27);
+ dbg.nr_wp = BMVAL(dbgdidr, 28, 31);
+
+ /* Allocate dbg state save space */
+ dbg.state = kzalloc(MAX_DBG_STATE_SIZE * sizeof(uint32_t), GFP_KERNEL);
+ if (!dbg.state) {
+ ret = -ENOMEM;
+ goto dbg_err;
+ }
+dbg_out:
+ return 0;
+dbg_err:
+ return ret;
+}
+arch_initcall(msm_jtag_dbg_init);
+
+static int __init msm_jtag_etm_init(void)
+{
+ int ret;
+ uint32_t etmidr;
+ uint32_t etmccr;
+
+ /* Vote for ETM power/clock enable */
+ etm_clk_enable();
+
+ /* Clear sticky bit in PDSR - required for ETMv3.3 (8660) */
+ etm_read(ETMPDSR);
+ isb();
+
+ /* Populate etm_ctx data */
+ etmidr = etm_read(ETMIDR);
+ etm.arch = BMVAL(etmidr, 4, 11);
+ etm.arch_supported = etm_arch_supported(etm.arch);
+ if (!etm.arch_supported) {
+ pr_info("etm arch %u not supported\n", etm.arch);
+ goto etm_out;
+ }
+ etmccr = etm_read(ETMCCR);
+ etm.nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
+ etm.nr_cntr = BMVAL(etmccr, 13, 15);
+ etm.nr_ext_inp = BMVAL(etmccr, 17, 19);
+ etm.nr_ext_out = BMVAL(etmccr, 20, 22);
+ etm.nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
+
+ /* Vote for ETM power/clock disable */
+ etm_clk_disable();
+
+ /* Allocate etm state save space */
+ etm.state = kzalloc(MAX_ETM_STATE_SIZE * sizeof(uint32_t), GFP_KERNEL);
+ if (!etm.state) {
+ ret = -ENOMEM;
+ goto etm_err;
+ }
+etm_out:
+ return 0;
+etm_err:
+ return ret;
+}
+arch_initcall(msm_jtag_etm_init);
diff --git a/arch/arm/mach-msm/qdss-debug.c b/arch/arm/mach-msm/qdss-debug.c
deleted file mode 100644
index b2d38b1..0000000
--- a/arch/arm/mach-msm/qdss-debug.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-#include <linux/smp.h>
-
-#include "qdss.h"
-
-#define debug_writel(debug, cpu, val, off) \
- __raw_writel((val), debug.base[cpu] + off)
-#define debug_readl(debug, cpu, off) \
- __raw_readl(debug.base[cpu] + off)
-
-#define DBGDIDR (0x000)
-#define DBGWFAR (0x018)
-#define DBGVCR (0x01C)
-#define DBGECR (0x024)
-#define DBGDTRRX (0x080)
-#define DBGITR (0x084)
-#define DBGDSCR (0x088)
-#define DBGDTRTX (0x08C)
-#define DBGDRCR (0x090)
-#define DBGEACR (0x094)
-#define DBGPCSR (0x0A0)
-#define DBGCIDSR (0x0A4)
-#define DBGVIDSR (0x0A8)
-#define DBGBVRm(n) (0x100 + (n * 4))
-#define DBGBCRm(n) (0x140 + (n * 4))
-#define DBGWVRm(n) (0x180 + (n * 4))
-#define DBGWCRm(n) (0x1C0 + (n * 4))
-#define DBGBXVRm(n) (0x240 + (n * 4))
-#define DBGOSLAR (0x300)
-#define DBGOSLSR (0x304)
-#define DBGPRCR (0x310)
-#define DBGPRSR (0x314)
-
-
-#define DEBUG_LOCK(cpu) \
-do { \
- mb(); \
- debug_writel(debug, cpu, MAGIC2, CS_LAR); \
-} while (0)
-#define DEBUG_UNLOCK(cpu) \
-do { \
- debug_writel(debug, cpu, MAGIC1, CS_LAR); \
- mb(); \
-} while (0)
-
-#define DEBUG_OS_LOCK(cpu) \
-do { \
- debug_writel(debug, cpu, MAGIC1, DBGOSLAR); \
- mb(); \
-} while (0)
-#define DEBUG_OS_UNLOCK(cpu) \
-do { \
- mb(); \
- debug_writel(debug, cpu, MAGIC2, DBGOSLAR); \
- mb(); \
-} while (0)
-
-#define MAX_DEBUG_REGS (90)
-#define MAX_STATE_SIZE (MAX_DEBUG_REGS * num_possible_cpus())
-#define DBGDSCR_MASK (0x6C30FC3C)
-
-struct debug_config {
- /* read only config register */
- uint32_t dbg_id;
- /* derived values */
- uint8_t nr_watch_pts;
- uint8_t nr_brk_pts;
- uint8_t nr_ctx_comp;
-};
-
-struct debug_ctx {
- struct debug_config cfg;
- void __iomem **base;
- uint32_t *state;
- struct device *dev;
-};
-
-static struct debug_ctx debug;
-
-static void debug_save_reg(int cpu)
-{
- uint32_t i;
- int j;
-
- DEBUG_UNLOCK(cpu);
- DEBUG_OS_LOCK(cpu);
-
- i = cpu * MAX_DEBUG_REGS;
-
- debug.state[i++] = debug_readl(debug, cpu, DBGWFAR);
- for (j = 0; j < debug.cfg.nr_brk_pts; j++) {
- debug.state[i++] = debug_readl(debug, cpu, DBGBCRm(j));
- debug.state[i++] = debug_readl(debug, cpu, DBGBVRm(j));
- }
- for (j = 0; j < debug.cfg.nr_ctx_comp; j++)
- debug.state[i++] = debug_readl(debug, cpu, DBGBXVRm(j));
- for (j = 0; j < debug.cfg.nr_watch_pts; j++) {
- debug.state[i++] = debug_readl(debug, cpu, DBGWVRm(j));
- debug.state[i++] = debug_readl(debug, cpu, DBGWCRm(j));
- }
- debug.state[i++] = debug_readl(debug, cpu, DBGVCR);
- debug.state[i++] = debug_readl(debug, cpu, CS_CLAIMSET);
- debug.state[i++] = debug_readl(debug, cpu, CS_CLAIMCLR);
- debug.state[i++] = debug_readl(debug, cpu, DBGDTRTX);
- debug.state[i++] = debug_readl(debug, cpu, DBGDTRRX);
- debug.state[i++] = debug_readl(debug, cpu, DBGDSCR);
-
- DEBUG_LOCK(cpu);
-}
-
-static void debug_restore_reg(int cpu)
-{
- uint32_t i;
- int j;
-
- DEBUG_UNLOCK(cpu);
- DEBUG_OS_LOCK(cpu);
-
- i = cpu * MAX_DEBUG_REGS;
-
- debug_writel(debug, cpu, debug.state[i++], DBGWFAR);
- for (j = 0; j < debug.cfg.nr_brk_pts; j++) {
- debug_writel(debug, cpu, debug.state[i++], DBGBCRm(j));
- debug_writel(debug, cpu, debug.state[i++], DBGBVRm(j));
- }
- for (j = 0; j < debug.cfg.nr_ctx_comp; j++)
- debug_writel(debug, cpu, debug.state[i++], DBGBXVRm(j));
- for (j = 0; j < debug.cfg.nr_watch_pts; j++) {
- debug_writel(debug, cpu, debug.state[i++], DBGWVRm(j));
- debug_writel(debug, cpu, debug.state[i++], DBGWCRm(j));
- }
- debug_writel(debug, cpu, debug.state[i++], DBGVCR);
- debug_writel(debug, cpu, debug.state[i++], CS_CLAIMSET);
- debug_writel(debug, cpu, debug.state[i++], CS_CLAIMCLR);
- debug_writel(debug, cpu, debug.state[i++], DBGDTRTX);
- debug_writel(debug, cpu, debug.state[i++], DBGDTRRX);
- debug_writel(debug, cpu, debug.state[i++] & DBGDSCR_MASK, DBGDSCR);
-
- DEBUG_OS_UNLOCK(cpu);
- DEBUG_LOCK(cpu);
-}
-
-/* msm_save_jtag_debug and msm_restore_jtag_debug should be fast
- *
- * These functions will be called either from:
- * 1. per_cpu idle thread context for idle power collapses.
- * 2. per_cpu idle thread context for hotplug/suspend power collapse for
- * nonboot cpus.
- * 3. suspend thread context for core0.
- *
- * In all cases we are guaranteed to be running on the same cpu for the
- * entire duration.
- */
-void msm_save_jtag_debug(void)
-{
- int cpu = smp_processor_id();
- debug_save_reg(cpu);
-}
-
-void msm_restore_jtag_debug(void)
-{
- int cpu = smp_processor_id();
- debug_restore_reg(cpu);
-}
-
-static void debug_cfg_ro_init(void)
-{
- /* use cpu 0 for setup */
- int cpu = 0;
-
- DEBUG_UNLOCK(cpu);
-
- debug.cfg.dbg_id = debug_readl(debug, cpu, DBGDIDR);
- debug.cfg.nr_ctx_comp = BMVAL(debug.cfg.dbg_id, 20, 23) + 1;
- debug.cfg.nr_brk_pts = BMVAL(debug.cfg.dbg_id, 24, 27) + 1;
- debug.cfg.nr_watch_pts = BMVAL(debug.cfg.dbg_id, 28, 31) + 1;
-
- DEBUG_LOCK(cpu);
-}
-
-static int __devinit debug_probe(struct platform_device *pdev)
-{
- int i, ret;
- struct resource *res;
-
- debug.base = kzalloc(pdev->num_resources * sizeof(void *), GFP_KERNEL);
- if (!debug.base) {
- ret = -ENOMEM;
- goto err_base_kzalloc;
- }
-
- for (i = 0; i < pdev->num_resources; i++) {
- res = platform_get_resource(pdev, IORESOURCE_MEM, i);
- if (!res) {
- ret = -EINVAL;
- goto err_res;
- }
-
- debug.base[i] = ioremap_nocache(res->start, resource_size(res));
- if (!debug.base[i]) {
- ret = -EINVAL;
- goto err_ioremap;
- }
- }
-
- debug.dev = &pdev->dev;
-
- debug.state = kzalloc(MAX_STATE_SIZE * sizeof(uint32_t), GFP_KERNEL);
- if (!debug.state) {
- ret = -ENOMEM;
- goto err_state_kzalloc;
- }
-
- debug_cfg_ro_init();
-
- dev_info(debug.dev, "Debug intialized.\n");
-
- return 0;
-
-err_state_kzalloc:
-err_ioremap:
-err_res:
- while (i) {
- iounmap(debug.base[i-1]);
- i--;
- }
- kfree(debug.base);
-err_base_kzalloc:
- return ret;
-}
-
-static int __devexit debug_remove(struct platform_device *pdev)
-{
- int i;
-
- kfree(debug.state);
- for (i = pdev->num_resources; i > 0; i--)
- iounmap(debug.base[i-1]);
- kfree(debug.base);
-
- return 0;
-}
-
-static struct platform_driver debug_driver = {
- .probe = debug_probe,
- .remove = __devexit_p(debug_remove),
- .driver = {
- .name = "msm_debug",
- },
-};
-
-static int __init debug_init(void)
-{
- return platform_driver_register(&debug_driver);
-}
-module_init(debug_init);
-
-static void __exit debug_exit(void)
-{
- platform_driver_unregister(&debug_driver);
-}
-module_exit(debug_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("Coresight Debug driver");
diff --git a/arch/arm/mach-msm/qdss-etb.c b/arch/arm/mach-msm/qdss-etb.c
index 16f8a5b..24419c6 100644
--- a/arch/arm/mach-msm/qdss-etb.c
+++ b/arch/arm/mach-msm/qdss-etb.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -56,11 +56,11 @@
#define ETB_LOCK() \
do { \
mb(); \
- etb_writel(etb, MAGIC2, CS_LAR); \
+ etb_writel(etb, 0x0, CS_LAR); \
} while (0)
#define ETB_UNLOCK() \
do { \
- etb_writel(etb, MAGIC1, CS_LAR); \
+ etb_writel(etb, CS_UNLOCK_MAGIC, CS_LAR); \
mb(); \
} while (0)
diff --git a/arch/arm/mach-msm/qdss-funnel.c b/arch/arm/mach-msm/qdss-funnel.c
index 290b418..c8b1f99 100644
--- a/arch/arm/mach-msm/qdss-funnel.c
+++ b/arch/arm/mach-msm/qdss-funnel.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -37,11 +37,11 @@
#define FUNNEL_LOCK(id) \
do { \
mb(); \
- funnel_writel(funnel, id, MAGIC2, CS_LAR); \
+ funnel_writel(funnel, id, 0x0, CS_LAR); \
} while (0)
#define FUNNEL_UNLOCK(id) \
do { \
- funnel_writel(funnel, id, MAGIC1, CS_LAR); \
+ funnel_writel(funnel, id, CS_UNLOCK_MAGIC, CS_LAR); \
mb(); \
} while (0)
diff --git a/arch/arm/mach-msm/qdss-ptm.c b/arch/arm/mach-msm/qdss-ptm.c
index 205e2b8..ce61b1d 100644
--- a/arch/arm/mach-msm/qdss-ptm.c
+++ b/arch/arm/mach-msm/qdss-ptm.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -100,32 +100,17 @@
#define ETMPDCR (0x310)
#define ETMPDSR (0x314)
-
#define PTM_LOCK(cpu) \
do { \
mb(); \
- ptm_writel(ptm, cpu, MAGIC2, CS_LAR); \
+ ptm_writel(ptm, cpu, 0x0, CS_LAR); \
} while (0)
#define PTM_UNLOCK(cpu) \
do { \
- ptm_writel(ptm, cpu, MAGIC1, CS_LAR); \
+ ptm_writel(ptm, cpu, CS_UNLOCK_MAGIC, CS_LAR); \
mb(); \
} while (0)
-#define PTM_OS_LOCK(cpu) \
-do { \
- ptm_writel(ptm, cpu, MAGIC1, ETMOSLAR); \
- mb(); \
-} while (0)
-#define PTM_OS_UNLOCK(cpu) \
-do { \
- mb(); \
- ptm_writel(ptm, cpu, MAGIC2, ETMOSLAR); \
- mb(); \
-} while (0)
-
-#define MAX_TRACE_REGS (78)
-#define MAX_STATE_SIZE (MAX_TRACE_REGS * num_possible_cpus())
/* Forward declarations */
static void ptm_cfg_rw_init(void);
@@ -189,7 +174,6 @@
struct ptm_ctx {
struct ptm_config cfg;
void __iomem *base;
- uint32_t *state;
bool trace_enabled;
struct wake_lock wake_lock;
struct pm_qos_request_list qos_req;
@@ -204,14 +188,6 @@
static struct ptm_ctx ptm;
-/* Memory mapped writes to clear os lock don't work */
-static void ptm_os_unlock(void *unused)
-{
- unsigned long value = 0x0;
-
- asm("mcr p14, 1, %0, c1, c0, 4\n\t" : : "r" (value));
- asm("isb\n\t");
-}
static int ptm_clock_enable(void)
{
@@ -260,6 +236,21 @@
clk_disable(ptm.qdss_at_clk);
}
+/* ETM clock is derived from the processor clock and gets enabled on a
+ * logical OR of below items on Krait (pass2 onwards):
+ * 1.CPMR[ETMCLKEN] is 1
+ * 2.ETMCR[PD] is 0
+ * 3.ETMPDCR[PU] is 1
+ * 4.Reset is asserted (core or debug)
+ * 5.APB memory mapped requests (eg. EDAP access)
+ *
+ * 1., 2. and 3. above are permanent enables whereas 4. and 5. are temporary
+ * enables
+ *
+ * We rely on 5. to be able to access ETMCR and then use 2. above for ETM
+ * clock vote in the driver and the save-restore code uses 1. above
+ * for its vote
+ */
static void ptm_set_powerdown(int cpu)
{
uint32_t etmcr;
@@ -308,66 +299,63 @@
WARN(count == 0, "timeout while clearing prog bit\n");
}
-static void __ptm_trace_enable(void)
+static void __ptm_trace_enable(int cpu)
{
- int i, cpu;
+ int i;
- for_each_online_cpu(cpu) {
- PTM_UNLOCK(cpu);
- ptm_clear_powerdown(cpu);
- ptm_set_prog(cpu);
+ PTM_UNLOCK(cpu);
+ /* Vote for ETM power/clock enable */
+ ptm_clear_powerdown(cpu);
+ ptm_set_prog(cpu);
- ptm_writel(ptm, cpu, ptm.cfg.main_control | BIT(10), ETMCR);
- ptm_writel(ptm, cpu, ptm.cfg.trigger_event, ETMTRIGGER);
- ptm_writel(ptm, cpu, ptm.cfg.te_start_stop_control, ETMTSSCR);
- ptm_writel(ptm, cpu, ptm.cfg.te_event, ETMTEEVR);
- ptm_writel(ptm, cpu, ptm.cfg.te_control, ETMTECR1);
- ptm_writel(ptm, cpu, ptm.cfg.fifofull_level, ETMFFLR);
- for (i = 0; i < ptm.cfg.nr_addr_comp; i++) {
- ptm_writel(ptm, cpu, ptm.cfg.addr_comp_value[i],
- ETMACVRn(i));
- ptm_writel(ptm, cpu, ptm.cfg.addr_comp_access_type[i],
+ ptm_writel(ptm, cpu, ptm.cfg.main_control | BIT(10), ETMCR);
+ ptm_writel(ptm, cpu, ptm.cfg.trigger_event, ETMTRIGGER);
+ ptm_writel(ptm, cpu, ptm.cfg.te_start_stop_control, ETMTSSCR);
+ ptm_writel(ptm, cpu, ptm.cfg.te_event, ETMTEEVR);
+ ptm_writel(ptm, cpu, ptm.cfg.te_control, ETMTECR1);
+ ptm_writel(ptm, cpu, ptm.cfg.fifofull_level, ETMFFLR);
+ for (i = 0; i < ptm.cfg.nr_addr_comp; i++) {
+ ptm_writel(ptm, cpu, ptm.cfg.addr_comp_value[i], ETMACVRn(i));
+ ptm_writel(ptm, cpu, ptm.cfg.addr_comp_access_type[i],
ETMACTRn(i));
- }
- for (i = 0; i < ptm.cfg.nr_cntr; i++) {
- ptm_writel(ptm, cpu, ptm.cfg.cntr_reload_value[i],
- ETMCNTRLDVRn(i));
- ptm_writel(ptm, cpu, ptm.cfg.cntr_enable_event[i],
- ETMCNTENRn(i));
- ptm_writel(ptm, cpu, ptm.cfg.cntr_reload_event[i],
- ETMCNTRLDEVRn(i));
- ptm_writel(ptm, cpu, ptm.cfg.cntr_value[i],
- ETMCNTVRn(i));
- }
- ptm_writel(ptm, cpu, ptm.cfg.seq_state_12_event, ETMSQ12EVR);
- ptm_writel(ptm, cpu, ptm.cfg.seq_state_21_event, ETMSQ21EVR);
- ptm_writel(ptm, cpu, ptm.cfg.seq_state_23_event, ETMSQ23EVR);
- ptm_writel(ptm, cpu, ptm.cfg.seq_state_32_event, ETMSQ32EVR);
- ptm_writel(ptm, cpu, ptm.cfg.seq_state_13_event, ETMSQ13EVR);
- ptm_writel(ptm, cpu, ptm.cfg.seq_state_31_event, ETMSQ31EVR);
- ptm_writel(ptm, cpu, ptm.cfg.current_seq_state, ETMSQR);
- for (i = 0; i < ptm.cfg.nr_ext_output; i++)
- ptm_writel(ptm, cpu, ptm.cfg.ext_output_event[i],
- ETMEXTOUTEVRn(i));
- for (i = 0; i < ptm.cfg.nr_context_id_comp; i++)
- ptm_writel(ptm, cpu, ptm.cfg.context_id_comp_value[i],
- ETMCIDCVRn(i));
- ptm_writel(ptm, cpu, ptm.cfg.context_id_comp_mask, ETMCIDCMR);
- ptm_writel(ptm, cpu, ptm.cfg.sync_freq, ETMSYNCFR);
- ptm_writel(ptm, cpu, ptm.cfg.extnd_ext_input_sel, ETMEXTINSELR);
- ptm_writel(ptm, cpu, ptm.cfg.ts_event, ETMTSEVR);
- ptm_writel(ptm, cpu, ptm.cfg.aux_control, ETMAUXCR);
- ptm_writel(ptm, cpu, cpu+1, ETMTRACEIDR);
- ptm_writel(ptm, cpu, ptm.cfg.vmid_comp_value, ETMVMIDCVR);
-
- ptm_clear_prog(cpu);
- PTM_LOCK(cpu);
}
+ for (i = 0; i < ptm.cfg.nr_cntr; i++) {
+ ptm_writel(ptm, cpu, ptm.cfg.cntr_reload_value[i],
+ ETMCNTRLDVRn(i));
+ ptm_writel(ptm, cpu, ptm.cfg.cntr_enable_event[i],
+ ETMCNTENRn(i));
+ ptm_writel(ptm, cpu, ptm.cfg.cntr_reload_event[i],
+ ETMCNTRLDEVRn(i));
+ ptm_writel(ptm, cpu, ptm.cfg.cntr_value[i], ETMCNTVRn(i));
+ }
+ ptm_writel(ptm, cpu, ptm.cfg.seq_state_12_event, ETMSQ12EVR);
+ ptm_writel(ptm, cpu, ptm.cfg.seq_state_21_event, ETMSQ21EVR);
+ ptm_writel(ptm, cpu, ptm.cfg.seq_state_23_event, ETMSQ23EVR);
+ ptm_writel(ptm, cpu, ptm.cfg.seq_state_32_event, ETMSQ32EVR);
+ ptm_writel(ptm, cpu, ptm.cfg.seq_state_13_event, ETMSQ13EVR);
+ ptm_writel(ptm, cpu, ptm.cfg.seq_state_31_event, ETMSQ31EVR);
+ ptm_writel(ptm, cpu, ptm.cfg.current_seq_state, ETMSQR);
+ for (i = 0; i < ptm.cfg.nr_ext_output; i++)
+ ptm_writel(ptm, cpu, ptm.cfg.ext_output_event[i],
+ ETMEXTOUTEVRn(i));
+ for (i = 0; i < ptm.cfg.nr_context_id_comp; i++)
+ ptm_writel(ptm, cpu, ptm.cfg.context_id_comp_value[i],
+ ETMCIDCVRn(i));
+ ptm_writel(ptm, cpu, ptm.cfg.context_id_comp_mask, ETMCIDCMR);
+ ptm_writel(ptm, cpu, ptm.cfg.sync_freq, ETMSYNCFR);
+ ptm_writel(ptm, cpu, ptm.cfg.extnd_ext_input_sel, ETMEXTINSELR);
+ ptm_writel(ptm, cpu, ptm.cfg.ts_event, ETMTSEVR);
+ ptm_writel(ptm, cpu, ptm.cfg.aux_control, ETMAUXCR);
+ ptm_writel(ptm, cpu, cpu+1, ETMTRACEIDR);
+ ptm_writel(ptm, cpu, ptm.cfg.vmid_comp_value, ETMVMIDCVR);
+
+ ptm_clear_prog(cpu);
+ PTM_LOCK(cpu);
}
static int ptm_trace_enable(void)
{
- int ret;
+ int ret, cpu;
ret = ptm_clock_enable();
if (ret)
@@ -388,9 +376,8 @@
/* enable ETB first to avoid loosing any trace data */
etb_enable();
funnel_enable(0x0, 0x3);
- ptm_os_unlock(NULL);
- smp_call_function(ptm_os_unlock, NULL, 1);
- __ptm_trace_enable();
+ for_each_online_cpu(cpu)
+ __ptm_trace_enable(cpu);
ptm.trace_enabled = true;
@@ -400,24 +387,23 @@
return 0;
}
-static void __ptm_trace_disable(void)
+static void __ptm_trace_disable(int cpu)
{
- int cpu;
+ PTM_UNLOCK(cpu);
+ ptm_set_prog(cpu);
- for_each_online_cpu(cpu) {
- PTM_UNLOCK(cpu);
- ptm_set_prog(cpu);
+ /* program trace enable to low by using always false event */
+ ptm_writel(ptm, cpu, 0x6F | BIT(14), ETMTEEVR);
- /* program trace enable to low by using always false event */
- ptm_writel(ptm, cpu, 0x6F | BIT(14), ETMTEEVR);
-
- ptm_set_powerdown(cpu);
- PTM_LOCK(cpu);
- }
+ /* Vote for ETM power/clock disable */
+ ptm_set_powerdown(cpu);
+ PTM_LOCK(cpu);
}
static void ptm_trace_disable(void)
{
+ int cpu;
+
wake_lock(&ptm.wake_lock);
/* 1. causes all online cpus to come out of idle PC
* 2. prevents idle PC until save restore flag is disabled atomically
@@ -428,7 +414,8 @@
*/
pm_qos_update_request(&ptm.qos_req, 0);
- __ptm_trace_disable();
+ for_each_online_cpu(cpu)
+ __ptm_trace_disable(cpu);
etb_dump();
etb_disable();
funnel_disable(0x0, 0x3);
@@ -597,151 +584,6 @@
.fops = &ptm_fops,
};
-static void ptm_save_reg(int cpu)
-{
- uint32_t i;
- int j;
-
- PTM_UNLOCK(cpu);
-
- i = cpu * MAX_TRACE_REGS;
-
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCR);
- ptm_set_prog(cpu);
-
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMTRIGGER);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMTSSCR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMTEEVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMTECR1);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMFFLR);
- for (j = 0; j < ptm.cfg.nr_addr_comp; j++) {
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMACVRn(j));
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMACTRn(j));
- }
- for (j = 0; j < ptm.cfg.nr_cntr; j++) {
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCNTRLDVRn(j));
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCNTENRn(j));
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCNTRLDEVRn(j));
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCNTVRn(j));
- }
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQ12EVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQ21EVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQ23EVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQ32EVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQ13EVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQ31EVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSQR);
- for (j = 0; j < ptm.cfg.nr_ext_output; j++)
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMEXTOUTEVRn(j));
- for (j = 0; j < ptm.cfg.nr_context_id_comp; j++)
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCIDCVRn(j));
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMCIDCMR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMSYNCFR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMEXTINSELR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMTSEVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMAUXCR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMTRACEIDR);
- ptm.state[i++] = ptm_readl(ptm, cpu, ETMVMIDCVR);
- ptm.state[i++] = ptm_readl(ptm, cpu, CS_CLAIMSET);
- ptm.state[i++] = ptm_readl(ptm, cpu, CS_CLAIMCLR);
-
- PTM_LOCK(cpu);
-}
-
-static void ptm_restore_reg(int cpu)
-{
- uint32_t i;
- int j;
-
- ptm_os_unlock(NULL);
- PTM_UNLOCK(cpu);
-
- i = cpu * MAX_TRACE_REGS;
-
- ptm_clear_powerdown(cpu);
- ptm_set_prog(cpu);
- /* Ensure prog bit doesn't get cleared since we have set it above.
- * Power down bit should already be clear in the saved state.
- */
- ptm_writel(ptm, cpu, ptm.state[i++] | BIT(10), ETMCR);
-
- ptm_writel(ptm, cpu, ptm.state[i++], ETMTRIGGER);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMTSSCR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMTEEVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMTECR1);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMFFLR);
- for (j = 0; j < ptm.cfg.nr_addr_comp; j++) {
- ptm_writel(ptm, cpu, ptm.state[i++], ETMACVRn(j));
- ptm_writel(ptm, cpu, ptm.state[i++], ETMACTRn(j));
- }
- for (j = 0; j < ptm.cfg.nr_cntr; j++) {
- ptm_writel(ptm, cpu, ptm.state[i++], ETMCNTRLDVRn(j));
- ptm_writel(ptm, cpu, ptm.state[i++], ETMCNTENRn(j));
- ptm_writel(ptm, cpu, ptm.state[i++], ETMCNTRLDEVRn(j));
- ptm_writel(ptm, cpu, ptm.state[i++], ETMCNTVRn(j));
- }
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQ12EVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQ21EVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQ23EVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQ32EVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQ13EVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQ31EVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSQR);
- for (j = 0; j < ptm.cfg.nr_ext_output; j++)
- ptm_writel(ptm, cpu, ptm.state[i++], ETMEXTOUTEVRn(j));
- for (j = 0; j < ptm.cfg.nr_context_id_comp; j++)
- ptm_writel(ptm, cpu, ptm.state[i++], ETMCIDCVRn(j));
- ptm_writel(ptm, cpu, ptm.state[i++], ETMCIDCMR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMSYNCFR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMEXTINSELR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMTSEVR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMAUXCR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMTRACEIDR);
- ptm_writel(ptm, cpu, ptm.state[i++], ETMVMIDCVR);
- ptm_writel(ptm, cpu, ptm.state[i++], CS_CLAIMSET);
- ptm_writel(ptm, cpu, ptm.state[i++], CS_CLAIMCLR);
-
- ptm_clear_prog(cpu);
-
- PTM_LOCK(cpu);
-}
-
-/* etm_save_reg_check and etm_restore_reg_check should be fast
- *
- * These functions will be called either from:
- * 1. per_cpu idle thread context for idle power collapses.
- * 2. per_cpu idle thread context for hotplug/suspend power collapse for
- * nonboot cpus.
- * 3. suspend thread context for core0.
- *
- * In all cases we are guaranteed to be running on the same cpu for the
- * entire duration.
- *
- * Another assumption is that etm registers won't change after trace_enabled
- * is set. Current usage model guarantees this doesn't happen.
- *
- * Also disabling all types of power_collapses when enabling and disabling
- * trace provides mutual exclusion to be able to safely access
- * ptm.trace_enabled here.
- */
-void etm_save_reg_check(void)
-{
- if (ptm.trace_enabled) {
- int cpu = smp_processor_id();
- ptm_save_reg(cpu);
- }
-}
-
-void etm_restore_reg_check(void)
-{
- if (ptm.trace_enabled) {
- int cpu = smp_processor_id();
- ptm_restore_reg(cpu);
- }
-}
-
static void ptm_cfg_rw_init(void)
{
int i;
@@ -781,14 +623,25 @@
ptm.cfg.vmid_comp_value = 0x00000000;
}
+/* Memory mapped writes to clear os lock not supported */
+static void ptm_os_unlock(void *unused)
+{
+ unsigned long value = 0x0;
+
+ asm("mcr p14, 1, %0, c1, c0, 4\n\t" : : "r" (value));
+ asm("isb\n\t");
+}
+
static void ptm_cfg_ro_init(void)
{
/* use cpu 0 for setup */
int cpu = 0;
+ /* Unlock OS lock first to allow memory mapped reads and writes */
ptm_os_unlock(NULL);
smp_call_function(ptm_os_unlock, NULL, 1);
PTM_UNLOCK(cpu);
+ /* Vote for ETM power/clock enable */
ptm_clear_powerdown(cpu);
ptm_set_prog(cpu);
@@ -809,6 +662,7 @@
ptm.cfg.fifofull_supported = BVAL(ptm.cfg.system_config, 8);
ptm.cfg.nr_procs_supported = BMVAL(ptm.cfg.system_config, 12, 14);
+ /* Vote for ETM power/clock disable */
ptm_set_powerdown(cpu);
PTM_LOCK(cpu);
}
@@ -832,12 +686,6 @@
ptm.dev = &pdev->dev;
- ptm.state = kzalloc(MAX_STATE_SIZE * sizeof(uint32_t), GFP_KERNEL);
- if (!ptm.state) {
- ret = -ENOMEM;
- goto err_kzalloc;
- }
-
ret = misc_register(&ptm_misc);
if (ret)
goto err_misc;
@@ -949,8 +797,6 @@
err_at:
misc_deregister(&ptm_misc);
err_misc:
- kfree(ptm.state);
-err_kzalloc:
iounmap(ptm.base);
err_ioremap:
err_res:
@@ -969,7 +815,6 @@
clk_put(ptm.qdss_pclkdbg_clk);
clk_put(ptm.qdss_at_clk);
misc_deregister(&ptm_misc);
- kfree(ptm.state);
iounmap(ptm.base);
return 0;
diff --git a/arch/arm/mach-msm/qdss-tpiu.c b/arch/arm/mach-msm/qdss-tpiu.c
index 60a8dd2..c6740e7 100644
--- a/arch/arm/mach-msm/qdss-tpiu.c
+++ b/arch/arm/mach-msm/qdss-tpiu.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -47,11 +47,11 @@
#define TPIU_LOCK() \
do { \
mb(); \
- tpiu_writel(tpiu, MAGIC2, CS_LAR); \
+ tpiu_writel(tpiu, 0x0, CS_LAR); \
} while (0)
#define TPIU_UNLOCK() \
do { \
- tpiu_writel(tpiu, MAGIC1, CS_LAR); \
+ tpiu_writel(tpiu, CS_UNLOCK_MAGIC, CS_LAR); \
mb(); \
} while (0)
diff --git a/arch/arm/mach-msm/qdss.h b/arch/arm/mach-msm/qdss.h
index 8d346c4..fef9460 100644
--- a/arch/arm/mach-msm/qdss.h
+++ b/arch/arm/mach-msm/qdss.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -15,7 +15,10 @@
#include <linux/bitops.h>
-/* Coresight management registers (0xF00-0xFCC) */
+/* Coresight management registers (0xF00-0xFCC)
+ * 0xFA0 - 0xFA4: Management registers in PFTv1.0
+ * Trace registers in PFTv1.1
+ */
#define CS_ITCTRL (0xF00)
#define CS_CLAIMSET (0xFA0)
#define CS_CLAIMCLR (0xFA4)
@@ -39,16 +42,22 @@
#define CS_CIDR2 (0xFF8)
#define CS_CIDR3 (0xFFC)
+/* DBGv7 with baseline CP14 registers implemented */
+#define ARM_DEBUG_ARCH_V7B (0x3)
+/* DBGv7 with all CP14 registers implemented */
+#define ARM_DEBUG_ARCH_V7 (0x4)
+#define ARM_DEBUG_ARCH_V7_1 (0x5)
+#define ETM_ARCH_V3_3 (0x23)
+#define PFT_ARCH_V1_1 (0x31)
-#define TIMEOUT_US 100
-#define MAGIC1 0xC5ACCE55
-#define MAGIC2 0x0
+#define TIMEOUT_US (100)
+#define OSLOCK_MAGIC (0xC5ACCE55)
+#define CS_UNLOCK_MAGIC (0xC5ACCE55)
#define BM(lsb, msb) ((BIT(msb) - BIT(lsb)) + BIT(msb))
#define BMVAL(val, lsb, msb) ((val & BM(lsb, msb)) >> lsb)
#define BVAL(val, n) ((val & BIT(n)) >> n)
-/* TODO: clean this up */
void etb_enable(void);
void etb_disable(void);
void etb_dump(void);
@@ -56,19 +65,12 @@
void funnel_enable(uint8_t id, uint32_t port_mask);
void funnel_disable(uint8_t id, uint32_t port_mask);
-#ifdef CONFIG_MSM_DEBUG_ACROSS_PC
-extern void msm_save_jtag_debug(void);
-extern void msm_restore_jtag_debug(void);
+#ifdef CONFIG_MSM_JTAG
+extern void msm_jtag_save_state(void);
+extern void msm_jtag_restore_state(void);
#else
-static inline void msm_save_jtag_debug(void) {}
-static inline void msm_restore_jtag_debug(void) {}
-#endif
-#ifdef CONFIG_MSM_TRACE_ACROSS_PC
-extern void etm_save_reg_check(void);
-extern void etm_restore_reg_check(void);
-#else
-static inline void etm_save_reg_check(void) {}
-static inline void etm_restore_reg_check(void) {}
+static inline void msm_jtag_save_state(void) {}
+static inline void msm_jtag_restore_state(void) {}
#endif
#endif