power: pm8921-bms: enable ccadc calibration
The ccadc needs to be calibrated every few minutes for accurate
battery charge estimation. The output of the calibration procedure
is gain and offset. The gain is used by the software while
the offset is programmed in a trim register. These trim values are
offset by bms every time it does an auto vsense read.
Change-Id: I20f6a7173321aa68967803d67c9a4813bcd75fae
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
diff --git a/drivers/power/pm8921-bms.c b/drivers/power/pm8921-bms.c
index fdbc819..751c6fc 100644
--- a/drivers/power/pm8921-bms.c
+++ b/drivers/power/pm8921-bms.c
@@ -23,6 +23,7 @@
#include <linux/bitops.h>
#include <linux/debugfs.h>
#include <linux/slab.h>
+#include <linux/delay.h>
#define BMS_CONTROL 0x224
#define BMS_OUTPUT0 0x230
@@ -35,14 +36,19 @@
#define CCADC_DATA1 0x245
#define CCADC_OFFSET_TRIM1 0x34A
#define CCADC_OFFSET_TRIM0 0x34B
+#define CCADC_FULLSCALE_TRIM1 0x34C
+#define CCADC_FULLSCALE_TRIM0 0x34D
#define ADC_ARB_SECP_CNTRL 0x190
#define ADC_ARB_SECP_AMUX_CNTRL 0x191
#define ADC_ARB_SECP_ANA_PARAM 0x192
+#define ADC_ARB_SECP_DIG_PARAM 0x193
#define ADC_ARB_SECP_RSV 0x194
#define ADC_ARB_SECP_DATA1 0x195
#define ADC_ARB_SECP_DATA0 0x196
+#define ADC_ARB_BMS_CNTRL 0x18D
+
enum pmic_bms_interrupts {
PM8921_BMS_SBI_WRITE_OK,
PM8921_BMS_CC_THR,
@@ -54,16 +60,6 @@
PM_BMS_MAX_INTS,
};
-/**
- * struct pm8921_bms_chip -device information
- * @dev: device pointer to access the parent
- * @dent: debugfs directory
- * @r_sense: batt sense resistance value
- * @i_test: peak current
- * @v_failure: battery dead voltage
- * @fcc: battery capacity
- *
- */
struct pm8921_bms_chip {
struct device *dev;
struct dentry *dent;
@@ -76,7 +72,9 @@
struct pc_temp_ocv_lut *pc_temp_ocv_lut;
struct pc_sf_lut *pc_sf_lut;
struct work_struct calib_hkadc_work;
+ struct delayed_work calib_ccadc_work;
unsigned int calib_delay_ms;
+ int ccadc_gain_uv;
unsigned int revision;
unsigned int xoadc_v0625;
unsigned int xoadc_v125;
@@ -389,11 +387,61 @@
* resolution (the value of a single bit) was changed after revision 2.0
* for more accurate readings
*/
- return (chip->revision < PM8XXX_REVISION_8901_2p0) ?
+ return (chip->revision < PM8XXX_REVISION_8921_2p0) ?
cc_to_microvolt_v1((s64)cc) :
cc_to_microvolt_v2((s64)cc);
}
+#define CCADC_READING_RESOLUTION_N_V1 1085069
+#define CCADC_READING_RESOLUTION_D_V1 100000
+#define CCADC_READING_RESOLUTION_N_V2 542535
+#define CCADC_READING_RESOLUTION_D_V2 100000
+static s64 ccadc_reading_to_microvolt_v1(s64 cc)
+{
+ return div_s64(cc * CCADC_READING_RESOLUTION_N_V1,
+ CCADC_READING_RESOLUTION_D_V1);
+}
+
+static s64 ccadc_reading_to_microvolt_v2(s64 cc)
+{
+ return div_s64(cc * CCADC_READING_RESOLUTION_N_V2,
+ CCADC_READING_RESOLUTION_D_V2);
+}
+
+static s64 ccadc_reading_to_microvolt(struct pm8921_bms_chip *chip, s64 cc)
+{
+ /*
+ * resolution (the value of a single bit) was changed after revision 2.0
+ * for more accurate readings
+ */
+ return (chip->revision < PM8XXX_REVISION_8921_2p0) ?
+ ccadc_reading_to_microvolt_v1((s64)cc) :
+ ccadc_reading_to_microvolt_v2((s64)cc);
+}
+
+static s64 microvolt_to_ccadc_reading_v1(s64 uv)
+{
+ return div_s64(uv * CCADC_READING_RESOLUTION_D_V1,
+ CCADC_READING_RESOLUTION_N_V1);
+}
+
+static s64 microvolt_to_ccadc_reading_v2(s64 uv)
+{
+ return div_s64(uv * CCADC_READING_RESOLUTION_D_V2,
+ CCADC_READING_RESOLUTION_N_V2);
+}
+
+static s64 microvolt_to_ccadc_reading(struct pm8921_bms_chip *chip, s64 cc)
+{
+ /*
+ * resolution (the value of a single bit) was changed after revision 2.0
+ * for more accurate readings
+ */
+ return (chip->revision < PM8XXX_REVISION_8921_2p0) ?
+ microvolt_to_ccadc_reading_v1((s64)cc) :
+ microvolt_to_ccadc_reading_v2((s64)cc);
+}
+
#define CC_READING_TICKS 55
#define SLEEP_CLK_HZ 32768
#define SECONDS_PER_HOUR 3600
@@ -403,6 +451,19 @@
SLEEP_CLK_HZ * SECONDS_PER_HOUR);
}
+#define GAIN_REFERENCE_UV 25000
+/*
+ * gain compensation for ccadc readings - common for vsense based and
+ * couloumb counter based readings
+ */
+static s64 cc_adjust_for_gain(struct pm8921_bms_chip *chip, s64 cc)
+{
+ if (chip->ccadc_gain_uv == 0)
+ return cc;
+
+ return div_s64(cc * GAIN_REFERENCE_UV, chip->ccadc_gain_uv);
+}
+
/* returns the signed value read from the hardware */
static int read_cc(struct pm8921_bms_chip *chip, int *result)
{
@@ -435,7 +496,9 @@
return rc;
}
*result = xoadc_reading_to_microvolt(reading);
- pr_debug("raw = %04x ocv_microV = %u\n", reading, *result);
+ pr_debug("raw = %04x ocv_uV = %u\n", reading, *result);
+ *result = adjust_xo_vbatt_reading(chip, *result);
+ pr_debug("after adj ocv_uV = %u\n", *result);
if (*result != 0)
last_ocv_uv = *result;
return 0;
@@ -468,8 +531,10 @@
pr_err("fail to read VSENSE_FOR_RBATT rc = %d\n", rc);
return rc;
}
- *result = cc_to_microvolt(chip, reading);
- pr_debug("raw = %04x vsense_for_r_microV = %u\n", reading, *result);
+ *result = ccadc_reading_to_microvolt(chip, reading);
+ pr_debug("raw = %04x vsense_for_r_uV = %u\n", reading, *result);
+ *result = cc_adjust_for_gain(chip, *result);
+ pr_debug("after adj vsense_for_r_uV = %u\n", *result);
return 0;
}
@@ -500,8 +565,10 @@
pr_err("fail to read VSENSE_AVG rc = %d\n", rc);
return rc;
}
- *result = cc_to_microvolt(chip, reading);
- pr_debug("read = %04x vsense = %d\n", reading, *result);
+ *result = ccadc_reading_to_microvolt(chip, reading);
+ pr_debug("raw = %04x vsense = %d\n", reading, *result);
+ *result = cc_adjust_for_gain(the_chip, (s64)*result);
+ pr_debug("after adj vsense = %d\n", *result);
return 0;
}
@@ -866,6 +933,7 @@
rc = read_cc(the_chip, coulumb_counter);
cc_voltage_uv = (int64_t)*coulumb_counter;
cc_voltage_uv = cc_to_microvolt(chip, cc_voltage_uv);
+ cc_voltage_uv = cc_adjust_for_gain(chip, cc_voltage_uv);
pr_debug("cc_voltage_uv = %lld microvolts\n", cc_voltage_uv);
cc_uvh = ccmicrovolt_to_uvh(cc_voltage_uv);
pr_debug("cc_uvh = %lld micro_volt_hour\n", cc_uvh);
@@ -1098,6 +1166,385 @@
calib_hkadc(chip);
}
+#define START_CONV_BIT BIT(7)
+#define EOC_CONV_BIT BIT(6)
+#define SEL_CCADC_BIT BIT(1)
+#define EN_ARB_BIT BIT(0)
+
+#define CCADC_CALIB_DIG_PARAM 0xE3
+#define CCADC_CALIB_RSV_GND 0x40
+#define CCADC_CALIB_RSV_25MV 0x80
+#define CCADC_CALIB_ANA_PARAM 0x1B
+#define SAMPLE_COUNT 16
+#define ADC_WAIT_COUNT 10
+
+#define CCADC_MAX_25MV 30000
+#define CCADC_MIN_25MV 20000
+#define CCADC_MAX_0UV -4000
+#define CCADC_MIN_0UV -7000
+
+#define CCADC_INTRINSIC_OFFSET 0xC000
+
+#define REG_SBI_CONFIG 0x04F
+#define PAGE3_ENABLE_MASK 0x6
+
+static int calib_ccadc_enable_trim_access(struct pm8921_bms_chip *chip,
+ u8 *sbi_config)
+{
+ u8 reg;
+ int rc;
+
+ rc = pm8xxx_readb(chip->dev->parent, REG_SBI_CONFIG, sbi_config);
+ if (rc) {
+ pr_err("error = %d reading sbi config reg\n", rc);
+ return rc;
+ }
+
+ reg = *sbi_config | PAGE3_ENABLE_MASK;
+ return pm8xxx_writeb(chip->dev->parent, REG_SBI_CONFIG, reg);
+}
+
+static int calib_ccadc_restore_trim_access(struct pm8921_bms_chip *chip,
+ u8 sbi_config)
+{
+ return pm8xxx_writeb(chip->dev->parent, REG_SBI_CONFIG, sbi_config);
+}
+
+static int calib_ccadc_enable_arbiter(struct pm8921_bms_chip *chip)
+{
+ int rc;
+
+ /* enable Arbiter, must be sent twice */
+ rc = pm_bms_masked_write(chip, ADC_ARB_SECP_CNTRL,
+ SEL_CCADC_BIT | EN_ARB_BIT, SEL_CCADC_BIT | EN_ARB_BIT);
+ if (rc < 0) {
+ pr_err("error = %d enabling arbiter for offset\n", rc);
+ return rc;
+ }
+ rc = pm_bms_masked_write(chip, ADC_ARB_SECP_CNTRL,
+ SEL_CCADC_BIT | EN_ARB_BIT, SEL_CCADC_BIT | EN_ARB_BIT);
+ if (rc < 0) {
+ pr_err("error = %d writing ADC_ARB_SECP_CNTRL\n", rc);
+ return rc;
+ }
+ return 0;
+}
+
+static int calib_start_conv(struct pm8921_bms_chip *chip,
+ u16 *result)
+{
+ int rc, i;
+ u8 data_msb, data_lsb, reg;
+
+ /* Start conversion */
+ rc = pm_bms_masked_write(chip, ADC_ARB_SECP_CNTRL,
+ START_CONV_BIT, START_CONV_BIT);
+ if (rc < 0) {
+ pr_err("error = %d starting offset meas\n", rc);
+ return rc;
+ }
+
+ /* Wait for End of conversion */
+ for (i = 0; i < ADC_WAIT_COUNT; i++) {
+ rc = pm8xxx_readb(chip->dev->parent,
+ ADC_ARB_SECP_CNTRL, ®);
+ if (rc < 0) {
+ pr_err("error = %d read eoc for offset\n", rc);
+ return rc;
+ }
+ if ((reg & (START_CONV_BIT | EOC_CONV_BIT)) != EOC_CONV_BIT)
+ msleep(60);
+ else
+ break;
+ }
+ if (i == ADC_WAIT_COUNT) {
+ pr_err("waited too long for offset eoc\n");
+ return rc;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_SECP_DATA0, &data_lsb);
+ if (rc < 0) {
+ pr_err("error = %d reading offset lsb\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_SECP_DATA1, &data_msb);
+ if (rc < 0) {
+ pr_err("error = %d reading offset msb\n", rc);
+ return rc;
+ }
+
+ *result = (data_msb << 8) | data_lsb;
+ return 0;
+}
+
+static int calib_ccadc_read_trim(struct pm8921_bms_chip *chip,
+ int addr, u8 *data_msb, u8 *data_lsb)
+{
+ int rc;
+ u8 sbi_config;
+
+ calib_ccadc_enable_trim_access(chip, &sbi_config);
+ rc = pm8xxx_readb(chip->dev->parent, addr, data_msb);
+ if (rc < 0) {
+ pr_err("error = %d read msb\n", rc);
+ return rc;
+ }
+ rc = pm8xxx_readb(chip->dev->parent, addr + 1, data_lsb);
+ if (rc < 0) {
+ pr_err("error = %d read lsb\n", rc);
+ return rc;
+ }
+ calib_ccadc_restore_trim_access(chip, sbi_config);
+ return 0;
+}
+
+static int calib_ccadc_read_gain_uv(struct pm8921_bms_chip *chip)
+{
+ s8 data_msb;
+ u8 data_lsb;
+ int rc, gain, offset;
+
+ rc = calib_ccadc_read_trim(chip, CCADC_FULLSCALE_TRIM1,
+ &data_msb, &data_lsb);
+ gain = (data_msb << 8) | data_lsb;
+
+ rc = calib_ccadc_read_trim(chip, CCADC_OFFSET_TRIM1,
+ &data_msb, &data_lsb);
+ offset = (data_msb << 8) | data_lsb;
+
+ pr_debug("raw gain trim = 0x%x offset trim =0x%x\n", gain, offset);
+ gain = ccadc_reading_to_microvolt(chip, (s64)gain - offset);
+ return gain;
+}
+
+#define CCADC_PROGRAM_TRIM_COUNT 10
+#define ADC_ARB_BMS_CNTRL_CCADC_SHIFT 4
+#define ADC_ARB_BMS_CNTRL_CONV_MASK 0x03
+#define BMS_CONV_IN_PROGRESS 0x2
+
+static int calib_ccadc_program_trim(struct pm8921_bms_chip *chip,
+ int addr, u8 data_msb, u8 data_lsb)
+{
+ int rc, i;
+ u8 cntrl, sbi_config;
+ bool in_progress;
+
+ calib_ccadc_enable_trim_access(chip, &sbi_config);
+
+ for (i = 0; i < CCADC_PROGRAM_TRIM_COUNT; i++) {
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_BMS_CNTRL, &cntrl);
+ if (rc < 0) {
+ pr_err("error = %d reading ADC_ARB_BMS_CNTRL\n", rc);
+ return rc;
+ }
+
+ /* break if a ccadc conversion is not happening */
+ in_progress = (((cntrl >> ADC_ARB_BMS_CNTRL_CCADC_SHIFT)
+ & ADC_ARB_BMS_CNTRL_CONV_MASK) == BMS_CONV_IN_PROGRESS);
+
+ if (!in_progress)
+ break;
+ }
+
+ if (in_progress) {
+ pr_err("conv in progress cannot write trim,returing EBUSY\n");
+ return -EBUSY;
+ }
+
+ rc = pm8xxx_writeb(chip->dev->parent, addr, data_msb);
+ if (rc < 0) {
+ pr_err("error = %d write msb = 0x%x\n", rc, data_msb);
+ return rc;
+ }
+ rc = pm8xxx_writeb(chip->dev->parent, addr + 1, data_lsb);
+ if (rc < 0) {
+ pr_err("error = %d write lsb = 0x%x\n", rc, data_lsb);
+ return rc;
+ }
+ calib_ccadc_restore_trim_access(chip, sbi_config);
+ return 0;
+}
+
+static void calib_ccadc(struct pm8921_bms_chip *chip)
+{
+ u8 data_msb, data_lsb, sec_cntrl;
+ int result_offset, voltage_offset, result_gain;
+ u16 result;
+ int i, rc;
+
+ rc = pm8xxx_readb(chip->dev->parent, ADC_ARB_SECP_CNTRL, &sec_cntrl);
+ if (rc < 0) {
+ pr_err("error = %d reading ADC_ARB_SECP_CNTRL\n", rc);
+ return;
+ }
+
+ rc = calib_ccadc_enable_arbiter(chip);
+ if (rc < 0) {
+ pr_err("error = %d enabling arbiter for offset\n", rc);
+ goto bail;
+ }
+
+ /*
+ * Set decimation ratio to 4k, lower ratio may be used in order to speed
+ * up, pending verification through bench
+ */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_DIG_PARAM,
+ CCADC_CALIB_DIG_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d writing ADC_ARB_SECP_DIG_PARAM\n", rc);
+ goto bail;
+ }
+
+ result_offset = 0;
+ for (i = 0; i < SAMPLE_COUNT; i++) {
+ /* Short analog inputs to CCADC internally to ground */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_RSV,
+ CCADC_CALIB_RSV_GND);
+ if (rc < 0) {
+ pr_err("error = %d selecting gnd voltage\n", rc);
+ goto bail;
+ }
+
+ /* Enable CCADC */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_ANA_PARAM,
+ CCADC_CALIB_ANA_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d enabling ccadc\n", rc);
+ goto bail;
+ }
+
+ rc = calib_start_conv(chip, &result);
+ if (rc < 0) {
+ pr_err("error = %d for zero volt measurement\n", rc);
+ goto bail;
+ }
+
+ result_offset += result;
+ }
+
+ result_offset = result_offset / SAMPLE_COUNT;
+
+ voltage_offset = ccadc_reading_to_microvolt(chip,
+ ((s64)result_offset - CCADC_INTRINSIC_OFFSET));
+
+ pr_err("offset result_offset = 0x%x, voltage = %d microVolts\n",
+ result_offset, voltage_offset);
+
+ /* Sanity Check */
+ if (voltage_offset > CCADC_MAX_0UV) {
+ pr_err("offset voltage = %d is huge limiting to %d\n",
+ voltage_offset, CCADC_MAX_0UV);
+ result_offset = CCADC_INTRINSIC_OFFSET
+ + microvolt_to_ccadc_reading(chip, (s64)CCADC_MAX_0UV);
+ } else if (voltage_offset < CCADC_MIN_0UV) {
+ pr_err("offset voltage = %d is too low limiting to %d\n",
+ voltage_offset, CCADC_MIN_0UV);
+ result_offset = CCADC_INTRINSIC_OFFSET
+ + microvolt_to_ccadc_reading(chip, (s64)CCADC_MIN_0UV);
+ }
+
+ data_msb = result_offset >> 8;
+ data_lsb = result_offset;
+
+ rc = calib_ccadc_program_trim(chip, CCADC_OFFSET_TRIM1,
+ data_msb, data_lsb);
+ if (rc) {
+ pr_err("error = %d programming offset trim\n", rc);
+ goto bail;
+ }
+
+ rc = calib_ccadc_enable_arbiter(chip);
+ if (rc < 0) {
+ pr_err("error = %d enabling arbiter for gain\n", rc);
+ goto bail;
+ }
+
+ /*
+ * Set decimation ratio to 4k, lower ratio may be used in order to speed
+ * up, pending verification through bench
+ */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_DIG_PARAM,
+ CCADC_CALIB_DIG_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d enabling decimation ration for gain\n", rc);
+ goto bail;
+ }
+
+ result_gain = 0;
+ for (i = 0; i < SAMPLE_COUNT; i++) {
+ rc = pm8xxx_writeb(chip->dev->parent,
+ ADC_ARB_SECP_RSV, CCADC_CALIB_RSV_25MV);
+ if (rc < 0) {
+ pr_err("error = %d selecting 25mV for gain\n", rc);
+ goto bail;
+ }
+
+ /* Enable CCADC */
+ rc = pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_ANA_PARAM,
+ CCADC_CALIB_ANA_PARAM);
+ if (rc < 0) {
+ pr_err("error = %d enabling ccadc\n", rc);
+ goto bail;
+ }
+
+ rc = calib_start_conv(chip, &result);
+ if (rc < 0) {
+ pr_err("error = %d for adc reading 25mV\n", rc);
+ goto bail;
+ }
+
+ result_gain += result;
+ }
+ result_gain = result_gain / SAMPLE_COUNT;
+
+ /*
+ * result_offset includes INTRINSIC OFFSET
+ * chip->ccadc_gain_uv will be the actual voltage
+ * measured for 25000UV
+ */
+ chip->ccadc_gain_uv = ccadc_reading_to_microvolt(chip,
+ ((s64)result_gain - result_offset));
+
+ pr_debug("gain result_gain = 0x%x, voltage = %d microVolts\n",
+ result_gain,
+ chip->ccadc_gain_uv);
+ /* Sanity Check */
+ if (chip->ccadc_gain_uv > CCADC_MAX_25MV) {
+ pr_err("gain voltage = %d is huge limiting to %d\n",
+ chip->ccadc_gain_uv, CCADC_MAX_25MV);
+ chip->ccadc_gain_uv = CCADC_MAX_25MV;
+ result_gain = result_offset +
+ microvolt_to_ccadc_reading(chip, CCADC_MAX_25MV);
+ } else if (chip->ccadc_gain_uv < CCADC_MIN_25MV) {
+ pr_err("gain voltage = %d is too low limiting to %d\n",
+ chip->ccadc_gain_uv, CCADC_MIN_25MV);
+ chip->ccadc_gain_uv = CCADC_MIN_25MV;
+ result_gain = result_offset +
+ microvolt_to_ccadc_reading(chip, CCADC_MIN_25MV);
+ }
+
+ data_msb = result_gain >> 8;
+ data_lsb = result_gain;
+ rc = calib_ccadc_program_trim(chip, CCADC_FULLSCALE_TRIM1,
+ data_msb, data_lsb);
+ if (rc)
+ pr_err("error = %d programming gain trim\n", rc);
+bail:
+ pm8xxx_writeb(chip->dev->parent, ADC_ARB_SECP_CNTRL, sec_cntrl);
+}
+
+static void calibrate_ccadc_work(struct work_struct *work)
+{
+ struct pm8921_bms_chip *chip = container_of(work,
+ struct pm8921_bms_chip, calib_ccadc_work.work);
+
+ calib_ccadc(chip);
+ schedule_delayed_work(&chip->calib_ccadc_work,
+ round_jiffies_relative(msecs_to_jiffies
+ (chip->calib_delay_ms)));
+}
+
int pm8921_bms_get_vsense_avg(int *result)
{
int rc = -EINVAL;
@@ -1119,6 +1566,7 @@
int pm8921_bms_get_battery_current(int *result)
{
unsigned long flags;
+ int vsense;
if (!the_chip) {
pr_err("called before initialization\n");
@@ -1131,12 +1579,13 @@
spin_lock_irqsave(&the_chip->bms_output_lock, flags);
pm_bms_lock_output_data(the_chip);
- read_vsense_avg(the_chip, result);
+ read_vsense_avg(the_chip, &vsense);
pm_bms_unlock_output_data(the_chip);
spin_unlock_irqrestore(&the_chip->bms_output_lock, flags);
- pr_debug("vsense=%d\n", *result);
+ pr_debug("vsense=%d\n", vsense);
/* cast for signed division */
- *result = *result / (int)the_chip->r_sense;
+ *result = vsense / (int)the_chip->r_sense;
+
return 0;
}
EXPORT_SYMBOL(pm8921_bms_get_battery_current);
@@ -1451,6 +1900,7 @@
CALC_PC,
CALC_SOC,
CALIB_HKADC,
+ CALIB_CCADC,
};
static int test_batt_temp = 5;
@@ -1526,6 +1976,11 @@
*val = 0;
calib_hkadc(the_chip);
break;
+ case CALIB_CCADC:
+ /* reading this will trigger calibration */
+ *val = 0;
+ calib_ccadc(the_chip);
+ break;
default:
ret = -EINVAL;
}
@@ -1677,6 +2132,8 @@
(void *)CALC_SOC, &calc_fops);
debugfs_create_file("calib_hkadc", 0644, chip->dent,
(void *)CALIB_HKADC, &calc_fops);
+ debugfs_create_file("calib_ccadc", 0644, chip->dent,
+ (void *)CALIB_CCADC, &calc_fops);
for (i = 0; i < ARRAY_SIZE(bms_irq_data); i++) {
if (chip->pmic_bms_irq[bms_irq_data[i].irq_id])
@@ -1725,23 +2182,29 @@
chip->revision = pm8xxx_get_revision(chip->dev->parent);
INIT_WORK(&chip->calib_hkadc_work, calibrate_hkadc_work);
- rc = pm8921_bms_hw_init(chip);
- if (rc) {
- pr_err("couldn't init hardware rc = %d\n", rc);
- goto free_chip;
- }
-
rc = request_irqs(chip, pdev);
if (rc) {
pr_err("couldn't register interrupts rc = %d\n", rc);
goto free_chip;
}
+ rc = pm8921_bms_hw_init(chip);
+ if (rc) {
+ pr_err("couldn't init hardware rc = %d\n", rc);
+ goto free_irqs;
+ }
+
platform_set_drvdata(pdev, chip);
the_chip = chip;
create_debugfs_entries(chip);
check_initial_ocv(chip);
+ chip->ccadc_gain_uv = calib_ccadc_read_gain_uv(chip);
+
+ INIT_DELAYED_WORK(&chip->calib_ccadc_work, calibrate_ccadc_work);
+ /* begin calibration only on chips > 2.0 */
+ if (chip->revision >= PM8XXX_REVISION_8921_2p0)
+ calibrate_ccadc_work(&(chip->calib_ccadc_work.work));
/* initial hkadc calibration */
schedule_work(&chip->calib_hkadc_work);
@@ -1755,6 +2218,8 @@
vbatt, last_ocv_uv);
return 0;
+free_irqs:
+ free_irqs(chip);
free_chip:
kfree(chip);
return rc;