)]}'
{
  "commit": "1ad77a876da48331451698cc4172c90ab9b6372f",
  "tree": "e5bbb4a782e5d6c98ff140fb2bf9a05759383a68",
  "parents": [
    "65846909d684d75906269df4f5f3474e1fef568b"
  ],
  "author": {
    "name": "Lennert Buytenhek",
    "email": "buytenh@wantstofly.org",
    "time": "Fri Sep 05 13:17:11 2008 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Sat Sep 06 13:13:44 2008 +0100"
  },
  "message": "[ARM] 5241/1: provide ioremap_wc()\n\nThis patch provides an ARM implementation of ioremap_wc().\n\nWe use different page table attributes depending on which CPU we\nare running on:\n\n- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four\n  possible mapping types (CB\u003d00/01/10/11).  We can\u0027t use any of the\n  cached memory types (CB\u003d10/11), since that breaks coherency with\n  peripheral devices.  Both CB\u003d00 and CB\u003d01 are suitable for _wc, and\n  CB\u003d01 (Uncached/Buffered) allows the hardware more freedom than\n  CB\u003d00, so we\u0027ll use that.\n\n  (The ARMv5 ARM seems to suggest that CB\u003d01 is allowed to delay stores\n  but isn\u0027t allowed to merge them, but there is no other mapping type\n  we can use that allows the hardware to delay and merge stores, so\n  we\u0027ll go with CB\u003d01.)\n\n- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight\n  difference that on these platforms, CB\u003d01 actually _does_ allow\n  merging stores.  (If you want noncoalescing bufferable behavior\n  on Xscale v1/v2, you need to use XCB\u003d101.)\n\n- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB\u003d00100\n  mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal\n  in ARMv6 parlance).\n\n  The ARMv6 ARM explicitly says that any accesses to Normal memory can\n  be merged, which makes Normal memory more suitable for _wc mappings\n  than Device or Strongly Ordered memory, as the latter two mapping\n  types are guaranteed to maintain transaction number, size and order.\n  We use the Uncached variety of Normal mappings for the same reason\n  that we can\u0027t use C\u003d1 mappings on ARMv5.\n\n  The xsc3 Architecture Specification documents TEXCB\u003d00100 as being\n  Uncacheable and allowing coalescing of writes, which is also just\n  what we need.\n\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@marvell.com\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "94a95d7fafd6cdaf887e26dcfad35dbe6590c39a",
      "old_mode": 33188,
      "old_path": "arch/arm/include/asm/io.h",
      "new_id": "71934856fc22c38ede7ab9f4a6c1380d9e1dad5d",
      "new_mode": 33188,
      "new_path": "arch/arm/include/asm/io.h"
    },
    {
      "type": "modify",
      "old_id": "06f583b13999c220ba835658c657460ccb1a5783",
      "old_mode": 33188,
      "old_path": "arch/arm/include/asm/mach/map.h",
      "new_id": "9eb936e49cc349564f651ea973f71e6cdd273ee9",
      "new_mode": 33188,
      "new_path": "arch/arm/include/asm/mach/map.h"
    },
    {
      "type": "modify",
      "old_id": "25d9a11eb61750ade3ba77abd7771068ebe668ee",
      "old_mode": 33188,
      "old_path": "arch/arm/mm/mmu.c",
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      "new_mode": 33188,
      "new_path": "arch/arm/mm/mmu.c"
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}