msm: idle-v7: Add a isb between CCSELR write and CCSIDR read
An isb is required after a CCSELR write to ensure that write takes
effect before reading CCSIDR. Without an isb, CCSIDR read could
correspond to a random CCSELR register.
CRs-fixed: 320585
Signed-off-by: Maheshkumar Sivasubramanian <msivasub@codeaurora.org>
Change-Id: Iab75cd5ff98cfdc0eeeb721ccd3b739ae1fcbd70
diff --git a/arch/arm/mach-msm/idle-v7.S b/arch/arm/mach-msm/idle-v7.S
index 8f57f88..40e13fa 100644
--- a/arch/arm/mach-msm/idle-v7.S
+++ b/arch/arm/mach-msm/idle-v7.S
@@ -93,6 +93,7 @@
ldr r0, [r0]
mov r1, #0
mcr p15, 2, r1, c0, c0, 0 /*CCSELR*/
+ isb
mrc p15, 1, r1, c0, c0, 0 /*CCSIDR*/
mov r2, #1
and r1, r2, r1, ASR #30 /* Check if the cache is write back */