commit 1dbe8eb73259468d18b886804f4f13e4b4da54d1
author Jordan Crouse <jcrouse@codeaurora.org> Mon Mar 25 14:30:55 2013 -0600
committer Gerrit - the friendly Code Review server <code-review@localhost> Mon Mar 25 14:14:08 2013 -0700
tree 8e85d549817c3f2bb15f3faa1236982d846d3a90
parent ad8936a74f3bec2bc96cbb6391ac84f2b20323db

msm: kgsl: a2xx: Check the right interrupt status bits

Check the actual interrupt status bits in a2xx_irq_pending instead
of reading the mask registers which were always set and returning
true. Troutslap for the original author (me).

CRs-fixed: 467381
Change-Id: Ic0dedbada1c5fa64548221718c1eaf9b6eaaa1e8
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

drivers/gpu/msm/adreno_a2xx.c

diff --git a/drivers/gpu/msm/adreno_a2xx.c b/drivers/gpu/msm/adreno_a2xx.c
index ba4e507..aa14330 100644
--- a/drivers/gpu/msm/adreno_a2xx.c
+++ b/drivers/gpu/msm/adreno_a2xx.c
@@ -1821,14 +1821,14 @@
 static unsigned int a2xx_irq_pending(struct adreno_device *adreno_dev)
 {
 	struct kgsl_device *device = &adreno_dev->dev;
-	unsigned int rbbm, cp, mh;
+	unsigned int status;
 
-	adreno_regread(device, REG_RBBM_INT_CNTL, &rbbm);
-	adreno_regread(device, REG_CP_INT_CNTL, &cp);
-	adreno_regread(device, MH_INTERRUPT_MASK, &mh);
+	adreno_regread(device, REG_MASTER_INT_SIGNAL, &status);
 
-	return ((rbbm & RBBM_INT_MASK) || (cp & CP_INT_MASK) ||
-		(mh & kgsl_mmu_get_int_mask())) ? 1 : 0;
+	return (status &
+		(MASTER_INT_SIGNAL__MH_INT_STAT |
+		 MASTER_INT_SIGNAL__CP_INT_STAT |
+		 MASTER_INT_SIGNAL__RBBM_INT_STAT)) ? 1 : 0;
 }
 
 static void a2xx_rb_init(struct adreno_device *adreno_dev,