msm: acpuclock-krait: Discard unused SoC-specific data by using __initdata
Refactor the initialization code so that datastructures that must be
kept are kmemduped and the rest are discarded after the kernel has
booted with the help of __initdata markings.
For a typically-compiled all-in-one kernel containing support for
msm8960, apq8064, msm8627 and msm8930, this allows 11.5K to be moved
from the .data to the .init.data section, with less than 10% of that
retained in dynamically-allocated memory (the exact amount varies
depending on the device the kernel is booted on).
Change-Id: I505eef8f10dc0e44bab15954b797252c3c408e50
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-8627.c b/arch/arm/mach-msm/acpuclock-8627.c
index 43176ef..8060803 100644
--- a/arch/arm/mach-msm/acpuclock-8627.c
+++ b/arch/arm/mach-msm/acpuclock-8627.c
@@ -27,7 +27,7 @@
#define LVL_NOM RPM_VREG_CORNER_NOMINAL
#define LVL_HIGH RPM_VREG_CORNER_HIGH
-static struct hfpll_data hfpll_data = {
+static struct hfpll_data hfpll_data __initdata = {
.mode_offset = 0x00,
.l_offset = 0x08,
.m_offset = 0x0C,
@@ -43,10 +43,9 @@
.vdd[HFPLL_VDD_NOM] = LVL_NOM,
};
-static struct scalable scalable[] = {
+static struct scalable scalable[] __initdata = {
[CPU0] = {
.hfpll_phys_base = 0x00903200,
- .hfpll_data = &hfpll_data,
.aux_clk_sel_phys = 0x02088014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x4501,
@@ -57,7 +56,6 @@
},
[CPU1] = {
.hfpll_phys_base = 0x00903300,
- .hfpll_data = &hfpll_data,
.aux_clk_sel_phys = 0x02098014,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x5501,
@@ -68,7 +66,6 @@
},
[L2] = {
.hfpll_phys_base = 0x00903400,
- .hfpll_data = &hfpll_data,
.aux_clk_sel_phys = 0x02011028,
.aux_clk_sel = 3,
.l2cpmr_iaddr = 0x0500,
@@ -76,7 +73,7 @@
},
};
-static struct msm_bus_paths bw_level_tbl[] = {
+static struct msm_bus_paths bw_level_tbl[] __initdata = {
[0] = BW_MBPS(640), /* At least 80 MHz on bus. */
[1] = BW_MBPS(1064), /* At least 133 MHz on bus. */
[2] = BW_MBPS(1600), /* At least 200 MHz on bus. */
@@ -84,7 +81,7 @@
[4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
};
-static struct msm_bus_scale_pdata bus_scale_data = {
+static struct msm_bus_scale_pdata bus_scale_data __initdata = {
.usecase = bw_level_tbl,
.num_usecases = ARRAY_SIZE(bw_level_tbl),
.active_only = 1,
@@ -92,7 +89,7 @@
};
/* TODO: Update vdd_dig, vdd_mem and bw when data is available. */
-static struct l2_level l2_freq_tbl[] = {
+static struct l2_level l2_freq_tbl[] __initdata = {
[0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, LVL_NOM, 1050000, 0 },
[1] = { { 384000, PLL_8, 0, 2, 0x00 }, LVL_NOM, 1050000, 1 },
[2] = { { 432000, HFPLL, 2, 0, 0x20 }, LVL_NOM, 1050000, 1 },
@@ -109,7 +106,7 @@
};
/* TODO: Update core voltages when data is available. */
-static struct acpu_level acpu_freq_tbl[] = {
+static struct acpu_level acpu_freq_tbl[] __initdata = {
{ 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
{ 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(5), 925000 },
@@ -126,14 +123,20 @@
{ 0, { 0 } }
};
-static struct acpuclk_krait_params acpuclk_8627_params = {
+static struct pvs_table pvs_tables[NUM_PVS] __initdata = {
+ [PVS_SLOW] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },
+ [PVS_NOMINAL] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },
+ [PVS_FAST] = { acpu_freq_tbl, sizeof(acpu_freq_tbl) },
+};
+
+static struct acpuclk_krait_params acpuclk_8627_params __initdata = {
.scalable = scalable,
- .pvs_acpu_freq_tbl[PVS_SLOW] = acpu_freq_tbl,
- .pvs_acpu_freq_tbl[PVS_NOMINAL] = acpu_freq_tbl,
- .pvs_acpu_freq_tbl[PVS_FAST] = acpu_freq_tbl,
+ .scalable_size = sizeof(scalable),
+ .hfpll_data = &hfpll_data,
+ .pvs_tables = pvs_tables,
.l2_freq_tbl = l2_freq_tbl,
- .l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl),
- .bus_scale_data = &bus_scale_data,
+ .l2_freq_tbl_size = sizeof(l2_freq_tbl),
+ .bus_scale = &bus_scale_data,
.qfprom_phys_base = 0x00700000,
};