)]}'
{
  "commit": "1f5826bd0ed6c0abec3da28dfffb8d12f0c2cb81",
  "tree": "734b934e846b902faf7d10d4ae104b27956eaeb0",
  "parents": [
    "0ec734c2b8b005667ffdaef8610d1024630683b0"
  ],
  "author": {
    "name": "Chris Dearman",
    "email": "chris@mips.com",
    "time": "Mon May 08 18:02:16 2006 +0100"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Wed Mar 12 14:14:40 2008 +0000"
  },
  "message": "[MIPS] Added missing cases for rdhwr emulation\n\nSome of these are architecturally required for R2 processors so lets try\nto be bit closer to the real thing.  This also provides access to the\nCPU cycle timer, even on multiprocessors.  In that aspect its currently\nbug compatible to what would happen on a R2-based SMP.\n\nSigned-off-by: Chris Dearman \u003cchris@mips.com\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fcae6675297273839812a4977c329ee6cb9e5899",
      "old_mode": 33188,
      "old_path": "arch/mips/kernel/traps.c",
      "new_id": "79cf7e913b9971f32c90a074f31fae636bebca5d",
      "new_mode": 33188,
      "new_path": "arch/mips/kernel/traps.c"
    }
  ]
}