| commit | 22e4b386af030940ad1ffbe913edb1265bc5156e | [log] [tgz] |
|---|---|---|
| author | Mayank Rana <mrana@codeaurora.org> | Wed Jan 11 21:35:00 2012 +0530 |
| committer | Mayank Rana <mrana@codeaurora.org> | Thu Jan 12 21:59:37 2012 +0530 |
| tree | 9e86866235e81ba276fc03d98ae3df99c063ca62 | |
| parent | cf61df743aa8c8541cfb15da2bd56644315d0f87 [diff] |
msm_serial_hs_lite: set uart clock rate to zero after disabling clock Change-Id: Ib6413cae2ee32cd5e6c049f4a22ee24b808cb2fa Signed-off-by: Mayank Rana <mrana@codeaurora.org>