)]}'
{
  "commit": "23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa",
  "tree": "56636558e8cdeee0739e7d8c82d66ffe625340b3",
  "parents": [
    "de4533a04eb4f66dbef71f59a9c118256b886823"
  ],
  "author": {
    "name": "Lennert Buytenhek",
    "email": "buytenh@wantstofly.org",
    "time": "Tue Mar 28 21:00:40 2006 +0100"
  },
  "committer": {
    "name": "Russell King",
    "email": "rmk+kernel@arm.linux.org.uk",
    "time": "Tue Mar 28 21:00:40 2006 +0100"
  },
  "message": "[ARM] 3377/2: add support for intel xsc3 core\n\nPatch from Lennert Buytenhek\n\nThis patch adds support for the new XScale v3 core.  This is an\nARMv5 ISA core with the following additions:\n\n- L2 cache\n- I/O coherency support (on select chipsets)\n- Low-Locality Reference cache attributes (replaces mini-cache)\n- Supersections (v6 compatible)\n- 36-bit addressing (v6 compatible)\n- Single instruction cache line clean/invalidate\n- LRU cache replacement (vs round-robin)\n\nI attempted to merge the XSC3 support into proc-xscale.S, but XSC3\ncores have separate errata and have to handle things like L2, so it\nis simpler to keep it separate.\n\nL2 cache support is currently a build option because the L2 enable\nbit must be set before we enable the MMU and there is no easy way to\ncapture command line parameters at this point.\n\nThere are still optimizations that can be done such as using LLR for\ncopypage (in theory using the exisiting mini-cache code) but those\ncan be addressed down the road.\n\nSigned-off-by: Deepak Saxena \u003cdsaxena@plexity.net\u003e\nSigned-off-by: Lennert Buytenhek \u003cbuytenh@wantstofly.org\u003e\nSigned-off-by: Russell King \u003crmk+kernel@arm.linux.org.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "99c0d323719a08bf7398031c5e0674b9aa424918",
      "old_mode": 33188,
      "old_path": "arch/arm/Makefile",
      "new_id": "0f571d3d2fa4b562fac6b76d79053aaa8d88f78e",
      "new_mode": 33188,
      "new_path": "arch/arm/Makefile"
    },
    {
      "type": "modify",
      "old_id": "e680c5fd93b51723313de2bcf97f49a006004eb5",
      "old_mode": 33188,
      "old_path": "arch/arm/mm/Kconfig",
      "new_id": "c55b739e10bafaa002df9c9a56b678b1cd9368f8",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/Kconfig"
    },
    {
      "type": "modify",
      "old_id": "ffe73ba2bf174d857738d986d1c30240d49bcf50",
      "old_mode": 33188,
      "old_path": "arch/arm/mm/Makefile",
      "new_id": "07a538505784068f949759f12e2dbec2253a1dd8",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "9a2cb4332b4c399ba7acfa111b6a63514e85e58f",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/copypage-xsc3.S"
    },
    {
      "type": "modify",
      "old_id": "ef8d30a185a97574657ee66d31134b9feec76363",
      "old_mode": 33188,
      "old_path": "arch/arm/mm/mm-armv.c",
      "new_id": "5e5d05bcad50012acee900405497cc3e2707916d",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/mm-armv.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f90513e9af0c30a05ffe96c12a8780f0eab414e2",
      "new_mode": 33188,
      "new_path": "arch/arm/mm/proc-xsc3.S"
    },
    {
      "type": "modify",
      "old_id": "09e19a783a51dd9339e5234fae2f65d01484742f",
      "old_mode": 33188,
      "old_path": "include/asm-arm/cacheflush.h",
      "new_id": "746be56b1b705e9a88819868e2fe01f44527c8fc",
      "new_mode": 33188,
      "new_path": "include/asm-arm/cacheflush.h"
    },
    {
      "type": "modify",
      "old_id": "da1d960387d9880f2fa602b028aca633719fc3f0",
      "old_mode": 33188,
      "old_path": "include/asm-arm/domain.h",
      "new_id": "f8ea2de4848ea7ae075836718342952a86cda1d0",
      "new_mode": 33188,
      "new_path": "include/asm-arm/domain.h"
    },
    {
      "type": "modify",
      "old_id": "416320d95419579178b82ea6aba75a381be7e706",
      "old_mode": 33188,
      "old_path": "include/asm-arm/page.h",
      "new_id": "a404d2bf0c68b9c0818efc75ca11571133444a77",
      "new_mode": 33188,
      "new_path": "include/asm-arm/page.h"
    },
    {
      "type": "modify",
      "old_id": "7bef2bf6be51333d67bde44a9f4bd6a0cf3500d5",
      "old_mode": 33188,
      "old_path": "include/asm-arm/proc-fns.h",
      "new_id": "106045edb8627846336531a560cb32b5608e85d1",
      "new_mode": 33188,
      "new_path": "include/asm-arm/proc-fns.h"
    },
    {
      "type": "modify",
      "old_id": "ec91d1ff032a5ebbeff161a91a83ef25932eb51e",
      "old_mode": 33188,
      "old_path": "include/asm-arm/system.h",
      "new_id": "95b3abf4851bb9cc70596edd3a239076910939ee",
      "new_mode": 33188,
      "new_path": "include/asm-arm/system.h"
    }
  ]
}