)]}'
{
  "commit": "2492c845189a961a92d8537a44d233e8e1e45c6d",
  "tree": "2c13ce489dc271d0391c468beb75e081b899f35c",
  "parents": [
    "39a8d7d13c113e4a98bfdfc45c7233188e4d715f"
  ],
  "author": {
    "name": "Dan Williams",
    "email": "dan.j.williams@intel.com",
    "time": "Tue Jan 02 13:52:31 2007 -0700"
  },
  "committer": {
    "name": "Dan Williams",
    "email": "dan.j.williams@intel.com",
    "time": "Fri Jul 13 08:06:19 2007 -0700"
  },
  "message": "iop3xx: surface the iop3xx DMA and AAU units to the iop-adma driver\n\nAdds the platform device definitions and the architecture specific support\nroutines (i.e. register initialization and descriptor formats) for the\niop-adma driver.\n\nChangelog:\n* add support for \u003e 1k zero sum buffer sizes\n* added dma/aau platform devices to iq80321 and iq80332 setup\n* fixed the calculation in iop_desc_is_aligned\n* support xor buffer sizes larger than 16MB\n* fix places where software descriptors are assumed to be contiguous, only\n  hardware descriptors are contiguous for up to a PAGE_SIZE buffer size\n* convert to async_tx\n* add interrupt support\n* add platform devices for 80219 boards\n* do not call platform register macros in driver code\n* remove switch() statements for compatible register offsets/layouts\n* change over to bitmap based capabilities\n* remove unnecessary ARM assembly statement\n* checkpatch.pl fixes\n* gpl v2 only correction\n* phys move to dma_async_tx_descriptor\n\nCc: Russell King \u003crmk@arm.linux.org.uk\u003e\nSigned-off-by: Dan Williams \u003cdan.j.williams@intel.com\u003e\n",
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