mmc: msm_sdcc: set RX_DATA_PEND bit during card read operation
Latest revision of SDCC4 controller have added RX_DATA_PEND bit under
MCI_DATA_CTL register. If this bit is set (1), data timeout counter
will start counting only after the Read command (with data) was sent
instead of counting from initialization of DPSM.
This patch sets this new control bit to 1 for card read operation.
As prior versions of SDCC controllers had this new bit as reserved bit,
we don't need any extra version check while using this bit. Which means
setting this bit in prior version of SDCC controllers will not have
any effect.
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
diff --git a/drivers/mmc/host/msm_sdcc.h b/drivers/mmc/host/msm_sdcc.h
index 9ad0bfa..3ffe65f 100644
--- a/drivers/mmc/host/msm_sdcc.h
+++ b/drivers/mmc/host/msm_sdcc.h
@@ -77,6 +77,7 @@
#define MCI_DPSM_DIRECTION (1 << 1)
#define MCI_DPSM_MODE (1 << 2)
#define MCI_DPSM_DMAENABLE (1 << 3)
+#define MCI_RX_DATA_PEND (1 << 20)
#define MMCIDATACNT 0x030
#define MMCISTATUS 0x034