ASoC: WCD9304: Fix register defaults for clock select
On any codec path bringup and teardown, the external clock
gate in digital block is not required to be changed.
Fix by setting the register value as default and not change
during bringup or teardown
Change-Id: Ie2c57cc9814f5e85bcc755679a29ed36d7f199a6
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
diff --git a/sound/soc/codecs/wcd9304.c b/sound/soc/codecs/wcd9304.c
index 3229bce..1fe28a2 100644
--- a/sound/soc/codecs/wcd9304.c
+++ b/sound/soc/codecs/wcd9304.c
@@ -1474,6 +1474,8 @@
pr_err("%s %d\n", __func__, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
+ snd_soc_update_bits(codec, SITAR_A_CDC_CLK_OTHR_RESET_CTL, 0x10,
+ 0x00);
snd_soc_update_bits(codec, SITAR_A_CDC_CLK_OTHR_CTL, 0x01,
0x01);
snd_soc_update_bits(codec, SITAR_A_CDC_CLSG_CTL, 0x08, 0x08);
@@ -1996,7 +1998,6 @@
snd_soc_update_bits(codec, SITAR_A_CLK_BUFF_EN1, 0x05, 0x05);
snd_soc_update_bits(codec, SITAR_A_CLK_BUFF_EN2, 0x02, 0x00);
snd_soc_update_bits(codec, SITAR_A_CLK_BUFF_EN2, 0x04, 0x04);
- snd_soc_update_bits(codec, SITAR_A_CDC_CLK_MCLK_CTL, 0x01, 0x01);
usleep_range(50, 50);
sitar->clock_active = true;
return 0;
@@ -2005,7 +2006,6 @@
{
struct sitar_priv *sitar = snd_soc_codec_get_drvdata(codec);
pr_err("%s\n", __func__);
- snd_soc_update_bits(codec, SITAR_A_CDC_CLK_MCLK_CTL, 0x01, 0x00);
snd_soc_update_bits(codec, SITAR_A_CLK_BUFF_EN2, 0x04, 0x00);
ndelay(160);
snd_soc_update_bits(codec, SITAR_A_CLK_BUFF_EN2, 0x02, 0x02);
@@ -3962,6 +3962,9 @@
/*enable HPF filter for TX paths */
{SITAR_A_CDC_TX1_MUX_CTL, 0x8, 0x0},
{SITAR_A_CDC_TX2_MUX_CTL, 0x8, 0x0},
+
+ /*enable External clock select*/
+ {SITAR_A_CDC_CLK_MCLK_CTL, 0x01, 0x01},
};
static void sitar_codec_init_reg(struct snd_soc_codec *codec)