msm: 8064: Enable crypto engine.
-add new clock - ce3_core_src_clk to 8064 target.
-ce3_p_clk and ce3_core_clk are derived from ce3_core_src_clk.
-ce3 core src clock expects that the driver(qce40) set the clock
rate before the clock is enabled.
-set ce3_core_src_clk rate to 100mhz.
-add new DMA channels for APQ8064.
Change-Id: I3f0897b43d5d58a60a1df4f61a241868b8b9a926
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
diff --git a/arch/arm/mach-msm/board-apq8064.c b/arch/arm/mach-msm/board-apq8064.c
index b131989..6662751 100644
--- a/arch/arm/mach-msm/board-apq8064.c
+++ b/arch/arm/mach-msm/board-apq8064.c
@@ -18,6 +18,8 @@
#include <linux/slimbus/slimbus.h>
#include <linux/msm_ssbi.h>
#include <linux/spi/spi.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_data/qcom_crypto_device.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
@@ -37,6 +39,7 @@
#include <mach/msm_memtypes.h>
#include <linux/bootmem.h>
#include <asm/setup.h>
+#include <mach/dma.h>
#include "msm_watchdog.h"
#include "board-apq8064.h"
@@ -443,6 +446,118 @@
apq8064_add_sdcc(3, apq8064_sdc3_pdata);
}
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+#define QCE_SIZE 0x10000
+#define QCE_0_BASE 0x11000000
+
+#define QCE_HW_KEY_SUPPORT 0
+#define QCE_SHA_HMAC_SUPPORT 1
+#define QCE_SHARE_CE_RESOURCE 3
+#define QCE_CE_SHARED 0
+
+static struct resource qcrypto_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV8064_CE_IN_CHAN,
+ .end = DMOV8064_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV8064_CE_IN_CRCI,
+ .end = DMOV8064_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV8064_CE_OUT_CRCI,
+ .end = DMOV8064_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static struct resource qcedev_resources[] = {
+ [0] = {
+ .start = QCE_0_BASE,
+ .end = QCE_0_BASE + QCE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "crypto_channels",
+ .start = DMOV8064_CE_IN_CHAN,
+ .end = DMOV8064_CE_OUT_CHAN,
+ .flags = IORESOURCE_DMA,
+ },
+ [2] = {
+ .name = "crypto_crci_in",
+ .start = DMOV8064_CE_IN_CRCI,
+ .end = DMOV8064_CE_IN_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+ [3] = {
+ .name = "crypto_crci_out",
+ .start = DMOV8064_CE_OUT_CRCI,
+ .end = DMOV8064_CE_OUT_CRCI,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+
+static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+static struct platform_device qcrypto_device = {
+ .name = "qcrypto",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcrypto_resources),
+ .resource = qcrypto_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcrypto_ce_hw_suppport,
+ },
+};
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+
+static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
+ .ce_shared = QCE_CE_SHARED,
+ .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
+ .hw_key_support = QCE_HW_KEY_SUPPORT,
+ .sha_hmac = QCE_SHA_HMAC_SUPPORT,
+};
+
+static struct platform_device qcedev_device = {
+ .name = "qce",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(qcedev_resources),
+ .resource = qcedev_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &qcedev_ce_hw_suppport,
+ },
+};
+#endif
+
+
#define MSM_SHARED_RAM_PHYS 0x80000000
static void __init apq8064_map_io(void)
{
@@ -526,6 +641,15 @@
&msm8064_device_saw_regulator_core1,
&msm8064_device_saw_regulator_core2,
&msm8064_device_saw_regulator_core3,
+#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
+ defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
+ &qcrypto_device,
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
+ defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
+ &qcedev_device,
+#endif
};
static struct platform_device *sim_devices[] __initdata = {