msm: 8064: Enable crypto engine.
-add new clock - ce3_core_src_clk to 8064 target.
-ce3_p_clk and ce3_core_clk are derived from ce3_core_src_clk.
-ce3 core src clock expects that the driver(qce40) set the clock
rate before the clock is enabled.
-set ce3_core_src_clk rate to 100mhz.
-add new DMA channels for APQ8064.
Change-Id: I3f0897b43d5d58a60a1df4f61a241868b8b9a926
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
diff --git a/arch/arm/mach-msm/clock-8960.c b/arch/arm/mach-msm/clock-8960.c
index aaf6c83..c16c2ee 100644
--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -5158,8 +5158,14 @@
CLK_LOOKUP("usb_fs_sys_clk", usb_fs1_sys_clk.c, NULL),
CLK_LOOKUP("iface_clk", ce1_p_clk.c, NULL),
CLK_LOOKUP("core_clk", ce1_core_clk.c, NULL),
- CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
+ CLK_LOOKUP("ref_clk", sata_phy_ref_clk.c, NULL),
CLK_LOOKUP("cfg_clk", sata_phy_cfg_clk.c, NULL),
+ CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qce.0"),
+ CLK_LOOKUP("iface_clk", ce3_p_clk.c, "qcrypto.0"),
+ CLK_LOOKUP("core_clk", ce3_core_clk.c, "qce.0"),
+ CLK_LOOKUP("core_clk", ce3_core_clk.c, "qcrypto.0"),
+ CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qce.0"),
+ CLK_LOOKUP("ce3_core_src_clk", ce3_src_clk.c, "qcrypto.0"),
CLK_LOOKUP("dma_bam_pclk", dma_bam_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi1_p_clk.c, NULL),
CLK_LOOKUP("iface_clk", gsbi2_p_clk.c, NULL),
@@ -5178,9 +5184,6 @@
CLK_LOOKUP("iface_clk", sdc3_p_clk.c, "msm_sdcc.3"),
CLK_LOOKUP("iface_clk", sdc4_p_clk.c, "msm_sdcc.4"),
CLK_LOOKUP("iface_clk", pcie_p_clk.c, NULL),
- CLK_LOOKUP("core_src_clk", ce3_src_clk.c, NULL),
- CLK_LOOKUP("core_clk", ce3_core_clk.c, NULL),
- CLK_LOOKUP("iface_clk", ce3_p_clk.c, NULL),
CLK_LOOKUP("core_clk", adm0_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", adm0_p_clk.c, "msm_dmov"),
CLK_LOOKUP("iface_clk", pmic_arb0_p_clk.c, NULL),