msm: 8064: Enable crypto engine.
-add new clock - ce3_core_src_clk to 8064 target.
-ce3_p_clk and ce3_core_clk are derived from ce3_core_src_clk.
-ce3 core src clock expects that the driver(qce40) set the clock
rate before the clock is enabled.
-set ce3_core_src_clk rate to 100mhz.
-add new DMA channels for APQ8064.
Change-Id: I3f0897b43d5d58a60a1df4f61a241868b8b9a926
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c
index 893933b..60a5aff 100644
--- a/drivers/crypto/msm/qce40.c
+++ b/drivers/crypto/msm/qce40.c
@@ -58,8 +58,9 @@
void __iomem *iobase; /* Virtual io base of CE HW */
unsigned int phy_iobase; /* Physical io base of CE HW */
- struct clk *ce_core_clk; /* Handle to CE clk */
- struct clk *ce_clk; /* Handle to CE clk */
+ struct clk *ce_core_src_clk; /* Handle to CE src clk*/
+ struct clk *ce_core_clk; /* Handle to CE clk */
+ struct clk *ce_clk; /* Handle to CE clk */
qce_comp_func_ptr_t qce_cb; /* qce callback function pointer */
@@ -2391,6 +2392,8 @@
struct resource *resource;
struct clk *ce_core_clk;
struct clk *ce_clk;
+ struct clk *ce_core_src_clk;
+ int ret = 0;
pce_dev = kzalloc(sizeof(struct qce_device), GFP_KERNEL);
if (!pce_dev) {
@@ -2461,10 +2464,26 @@
goto err;
}
+ /* Get CE3 src core clk. */
+ ce_core_src_clk = clk_get(pce_dev->pdev, "ce3_core_src_clk");
+ if (!IS_ERR(ce_core_src_clk)) {
+ pce_dev->ce_core_src_clk = ce_core_src_clk;
+
+ /* Set the core src clk @100Mhz */
+ ret = clk_set_rate(pce_dev->ce_core_src_clk, 100000000);
+ if (ret) {
+ clk_put(pce_dev->ce_core_src_clk);
+ goto err;
+ }
+ } else
+ pce_dev->ce_core_src_clk = NULL;
+
/* Get CE core clk */
ce_core_clk = clk_get(pce_dev->pdev, "core_clk");
if (IS_ERR(ce_core_clk)) {
*rc = PTR_ERR(ce_core_clk);
+ if (pce_dev->ce_core_src_clk != NULL)
+ clk_put(pce_dev->ce_core_src_clk);
goto err;
}
pce_dev->ce_core_clk = ce_core_clk;
@@ -2472,6 +2491,8 @@
ce_clk = clk_get(pce_dev->pdev, "iface_clk");
if (IS_ERR(ce_clk)) {
*rc = PTR_ERR(ce_clk);
+ if (pce_dev->ce_core_src_clk != NULL)
+ clk_put(pce_dev->ce_core_src_clk);
clk_put(pce_dev->ce_core_clk);
goto err;
}
@@ -2480,6 +2501,8 @@
/* Enable CE core clk */
*rc = clk_enable(pce_dev->ce_core_clk);
if (*rc) {
+ if (pce_dev->ce_core_src_clk != NULL)
+ clk_put(pce_dev->ce_core_src_clk);
clk_put(pce_dev->ce_core_clk);
clk_put(pce_dev->ce_clk);
goto err;
@@ -2488,6 +2511,8 @@
*rc = clk_enable(pce_dev->ce_clk);
if (*rc) {
clk_disable(pce_dev->ce_core_clk);
+ if (pce_dev->ce_core_src_clk != NULL)
+ clk_put(pce_dev->ce_core_src_clk);
clk_put(pce_dev->ce_core_clk);
clk_put(pce_dev->ce_clk);
goto err;
@@ -2539,6 +2564,9 @@
clk_disable(pce_dev->ce_clk);
clk_disable(pce_dev->ce_core_clk);
+ if (pce_dev->ce_core_src_clk != NULL)
+ clk_put(pce_dev->ce_core_src_clk);
+
clk_put(pce_dev->ce_clk);
clk_put(pce_dev->ce_core_clk);
@@ -2571,4 +2599,4 @@
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
MODULE_DESCRIPTION("Crypto Engine driver");
-MODULE_VERSION("2.13");
+MODULE_VERSION("2.14");