msm: msm_iomap: Unify iomap for 7x30 with 7K & 8K

Iomap for 7x30 is combined with 8K and 7k, this will allow us to reuse
the already defined static mappings.

Change-Id: I4f26cd420012028f018611c0ac27a02951404c8f
Signed-off-by: Taniya Das <tdas@codeaurora.org>
diff --git a/arch/arm/mach-msm/acpuclock-7x30.c b/arch/arm/mach-msm/acpuclock-7x30.c
index f2fb292..598b7c5 100644
--- a/arch/arm/mach-msm/acpuclock-7x30.c
+++ b/arch/arm/mach-msm/acpuclock-7x30.c
@@ -34,8 +34,8 @@
 #include "acpuclock.h"
 #include "spm.h"
 
-#define SCSS_CLK_CTL_ADDR	(MSM_ACC_BASE + 0x04)
-#define SCSS_CLK_SEL_ADDR	(MSM_ACC_BASE + 0x08)
+#define SCSS_CLK_CTL_ADDR	(MSM_ACC0_BASE + 0x04)
+#define SCSS_CLK_SEL_ADDR	(MSM_ACC0_BASE + 0x08)
 
 #define PLL2_L_VAL_ADDR		(MSM_CLK_CTL_BASE + 0x33C)
 #define PLL2_M_VAL_ADDR		(MSM_CLK_CTL_BASE + 0x340)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index b750b7e..1e4ebdcd 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -6317,7 +6317,7 @@
 }
 
 static struct msm_spm_platform_data msm_spm_data __initdata = {
-	.reg_base_addr = MSM_SAW_BASE,
+	.reg_base_addr = MSM_SAW0_BASE,
 
 	.reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
 	.reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 89c8aaf..e0c23fa 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -96,8 +96,8 @@
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
-		.start	= MSM_UART1_PHYS,
-		.end	= MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
+		.start	= MSM7X30_UART1_PHYS,
+		.end	= MSM7X30_UART1_PHYS + MSM7X30_UART1_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
@@ -109,8 +109,8 @@
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
-		.start	= MSM_UART2_PHYS,
-		.end	= MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
+		.start	= MSM7X30_UART2_PHYS,
+		.end	= MSM7X30_UART2_PHYS + MSM7X30_UART2_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 		.name  = "uart_resource"
 	},
@@ -123,8 +123,8 @@
 		.flags	= IORESOURCE_IRQ,
 	},
 	{
-		.start	= MSM_UART3_PHYS,
-		.end	= MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
+		.start	= MSM7X30_UART3_PHYS,
+		.end	= MSM7X30_UART3_PHYS + MSM7X30_UART3_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
@@ -626,7 +626,7 @@
 		.smd_int.dev_id = 0,
 
 		.smd_int.out_bit_pos =  1 << 0,
-		.smd_int.out_base = (void __iomem *)MSM_GCC_BASE,
+		.smd_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
 		.smd_int.out_offset = 0x8,
 
 		.smsm_int.irq_name = "a9_m2a_5",
@@ -636,7 +636,7 @@
 		.smsm_int.dev_id = 0,
 
 		.smsm_int.out_bit_pos =  1 << 5,
-		.smsm_int.out_base = (void __iomem *)MSM_GCC_BASE,
+		.smsm_int.out_base = (void __iomem *)MSM_APCS_GCC_BASE,
 		.smsm_int.out_offset = 0x8,
 
 	}
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index acd668b..10b3374 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2008-2010, 2012 Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -35,68 +35,52 @@
  *
  */
 
-#define MSM_VIC_BASE          IOMEM(0xFA000000)
-#define MSM_VIC_PHYS          0xC0080000
-#define MSM_VIC_SIZE          SZ_4K
+#define MSM7X30_VIC_PHYS		0xC0080000
+#define MSM7X30_VIC_SIZE		SZ_4K
 
-#define MSM_CSR_BASE          IOMEM(0xFA001000)
-#define MSM_CSR_PHYS          0xC0100000
-#define MSM_CSR_SIZE          SZ_4K
+#define MSM7X30_CSR_PHYS		0xC0100000
+#define MSM7X30_CSR_SIZE		SZ_4K
 
-#define MSM_TMR_PHYS          MSM_CSR_PHYS
-#define MSM_TMR_BASE          MSM_CSR_BASE
-#define MSM_TMR_SIZE          SZ_4K
+#define MSM7X30_TMR_PHYS		MSM7X30_CSR_PHYS
+#define MSM7X30_TMR_SIZE		SZ_4K
 
-#define MSM_GPIO1_BASE        IOMEM(0xFA003000)
-#define MSM_GPIO1_PHYS        0xAC001000
-#define MSM_GPIO1_SIZE        SZ_4K
+#define MSM7X30_GPIO1_PHYS		0xAC001000
+#define MSM7X30_GPIO1_SIZE		SZ_4K
 
-#define MSM_GPIO2_BASE        IOMEM(0xFA004000)
-#define MSM_GPIO2_PHYS        0xAC101000
-#define MSM_GPIO2_SIZE        SZ_4K
+#define MSM7X30_GPIO2_PHYS		0xAC101000
+#define MSM7X30_GPIO2_SIZE		SZ_4K
 
-#define MSM_CLK_CTL_BASE      IOMEM(0xFA005000)
-#define MSM_CLK_CTL_PHYS      0xAB800000
-#define MSM_CLK_CTL_SIZE      SZ_4K
+#define MSM7X30_CLK_CTL_PHYS		0xAB800000
+#define MSM7X30_CLK_CTL_SIZE		SZ_4K
 
-#define MSM_CLK_CTL_SH2_BASE  IOMEM(0xFA006000)
-#define MSM_CLK_CTL_SH2_PHYS  0xABA01000
-#define MSM_CLK_CTL_SH2_SIZE  SZ_4K
+#define MSM7X30_CLK_CTL_SH2_PHYS	0xABA01000
+#define MSM7X30_CLK_CTL_SH2_SIZE	SZ_4K
 
-#define MSM_ACC_BASE          IOMEM(0xFA007000)
-#define MSM_ACC_PHYS          0xC0101000
-#define MSM_ACC_SIZE          SZ_4K
+#define MSM7X30_ACC0_PHYS		0xC0101000
+#define MSM7X30_ACC0_SIZE		SZ_4K
 
-#define MSM_SAW_BASE          IOMEM(0xFA008000)
-#define MSM_SAW_PHYS          0xC0102000
-#define MSM_SAW_SIZE          SZ_4K
+#define MSM7X30_SAW0_PHYS		0xC0102000
+#define MSM7X30_SAW0_SIZE		SZ_4K
 
-#define MSM_GCC_BASE	      IOMEM(0xFA009000)
-#define MSM_GCC_PHYS	      0xC0182000
-#define MSM_GCC_SIZE	      SZ_4K
+#define MSM7X30_APCS_GCC_PHYS		0xC0182000
+#define MSM7X30_APCS_GCC_SIZE		SZ_4K
 
-#define MSM_TCSR_BASE	      IOMEM(0xFA00A000)
-#define MSM_TCSR_PHYS	      0xAB600000
-#define MSM_TCSR_SIZE	      SZ_4K
+#define MSM7X30_TCSR_PHYS		0xAB600000
+#define MSM7X30_TCSR_SIZE		SZ_4K
 
-#define MSM_SHARED_RAM_BASE   IOMEM(0xFA100000)
-#define MSM_SHARED_RAM_SIZE   SZ_1M
+#define MSM7X30_UART1_PHYS		0xACA00000
+#define MSM7X30_UART1_SIZE		SZ_4K
 
-#define MSM_UART1_PHYS        0xACA00000
-#define MSM_UART1_SIZE        SZ_4K
+#define MSM7X30_UART2_PHYS		0xACB00000
+#define MSM7X30_UART2_SIZE		SZ_4K
 
-#define MSM_UART2_PHYS        0xACB00000
-#define MSM_UART2_SIZE        SZ_4K
+#define MSM7X30_UART3_PHYS		0xACC00000
+#define MSM7X30_UART3_SIZE		SZ_4K
 
-#define MSM_UART3_PHYS        0xACC00000
-#define MSM_UART3_SIZE        SZ_4K
+#define MSM7X30_MDC_PHYS		0xAA500000
+#define MSM7X30_MDC_SIZE		SZ_1M
 
-#define MSM_MDC_BASE	      IOMEM(0xFA200000)
-#define MSM_MDC_PHYS	      0xAA500000
-#define MSM_MDC_SIZE	      SZ_1M
-
-#define MSM_AD5_BASE          IOMEM(0xFA300000)
-#define MSM_AD5_PHYS          0xA7000000
-#define MSM_AD5_SIZE          (SZ_1M*13)
+#define MSM7X30_AD5_PHYS		0xA7000000
+#define MSM7X30_AD5_SIZE		(SZ_1M*13)
 
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 27965d3..382ea5b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -49,7 +49,7 @@
 	defined(CONFIG_ARCH_MSM8930) || defined(CONFIG_ARCH_MSM9615) || \
 	defined(CONFIG_ARCH_MSMCOPPER) || defined(CONFIG_ARCH_MSM7X27) || \
 	defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X01A) || \
-	defined(CONFIG_ARCH_MSM8625)
+	defined(CONFIG_ARCH_MSM8625) || defined(CONFIG_ARCH_MSM7X30)
 
 /* Unified iomap */
 
@@ -88,6 +88,7 @@
 #define MSM_GPIO2_BASE		IOMEM(0xFA103000)	/*  4K */
 #define MSM_SCU_BASE		IOMEM(0xFA104000)	/*  4K */
 #define MSM_CFG_CTL_BASE	IOMEM(0xFA105000)	/*  4K */
+#define MSM_CLK_CTL_SH2_BASE	IOMEM(0xFA106000)	/*  4K */
 #define MSM_MDC_BASE		IOMEM(0xFA400000)	/*  1M */
 #define MSM_AD5_BASE		IOMEM(0xFA900000)	/*  13M (D00000)
 							  0xFB600000 */
@@ -96,13 +97,15 @@
 #define MSM8625_SECONDARY_PHYS		0x0FE00000
 
 
-#if defined(CONFIG_ARCH_MSM9615) || defined(CONFIG_ARCH_MSM7X27)
+#if defined(CONFIG_ARCH_MSM9615) || defined(CONFIG_ARCH_MSM7X27) \
+	|| defined(CONFIG_ARCH_MSM7X30)
 #define MSM_SHARED_RAM_SIZE	SZ_1M
 #else
 #define MSM_SHARED_RAM_SIZE	SZ_2M
 #endif
 
 #include "msm_iomap-7xxx.h"
+#include "msm_iomap-7x30.h"
 #include "msm_iomap-8625.h"
 #include "msm_iomap-8960.h"
 #include "msm_iomap-8930.h"
@@ -112,10 +115,7 @@
 
 #else
 /* Legacy single-target iomap */
-
-#if defined(CONFIG_ARCH_MSM7X30)
-#include "msm_iomap-7x30.h"
-#elif defined(CONFIG_ARCH_QSD8X50)
+#if defined(CONFIG_ARCH_QSD8X50)
 #include "msm_iomap-8x50.h"
 #elif defined(CONFIG_ARCH_MSM8X60)
 #include "msm_iomap-8x60.h"
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index bad8237..063f6bd 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -314,19 +314,19 @@
 
 #ifdef CONFIG_ARCH_MSM7X30
 static struct map_desc msm7x30_io_desc[] __initdata = {
-	MSM_DEVICE(VIC),
-	MSM_DEVICE(CSR),
-	MSM_DEVICE(TMR),
-	MSM_DEVICE(GPIO1),
-	MSM_DEVICE(GPIO2),
-	MSM_DEVICE(CLK_CTL),
-	MSM_DEVICE(CLK_CTL_SH2),
-	MSM_DEVICE(AD5),
-	MSM_DEVICE(MDC),
-	MSM_DEVICE(ACC),
-	MSM_DEVICE(SAW),
-	MSM_DEVICE(GCC),
-	MSM_DEVICE(TCSR),
+	MSM_CHIP_DEVICE(VIC, MSM7X30),
+	MSM_CHIP_DEVICE(CSR, MSM7X30),
+	MSM_CHIP_DEVICE(TMR, MSM7X30),
+	MSM_CHIP_DEVICE(GPIO1, MSM7X30),
+	MSM_CHIP_DEVICE(GPIO2, MSM7X30),
+	MSM_CHIP_DEVICE(CLK_CTL, MSM7X30),
+	MSM_CHIP_DEVICE(CLK_CTL_SH2, MSM7X30),
+	MSM_CHIP_DEVICE(AD5, MSM7X30),
+	MSM_CHIP_DEVICE(MDC, MSM7X30),
+	MSM_CHIP_DEVICE(ACC0, MSM7X30),
+	MSM_CHIP_DEVICE(SAW0, MSM7X30),
+	MSM_CHIP_DEVICE(APCS_GCC, MSM7X30),
+	MSM_CHIP_DEVICE(TCSR, MSM7X30),
 #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
 	defined(CONFIG_DEBUG_MSM_UART3)
 	MSM_DEVICE(DEBUG_UART),
diff --git a/arch/arm/mach-msm/pm2.c b/arch/arm/mach-msm/pm2.c
index 4d63b6d..6b026ac 100644
--- a/arch/arm/mach-msm/pm2.c
+++ b/arch/arm/mach-msm/pm2.c
@@ -420,8 +420,8 @@
  *****************************************************************************/
 
 #if defined(CONFIG_ARCH_MSM7X30)
-#define APPS_CLK_SLEEP_EN (MSM_GCC_BASE + 0x020)
-#define APPS_PWRDOWN      (MSM_ACC_BASE + 0x01c)
+#define APPS_CLK_SLEEP_EN (MSM_APCS_GCC_BASE + 0x020)
+#define APPS_PWRDOWN      (MSM_ACC0_BASE + 0x01c)
 #define APPS_SECOP        (MSM_TCSR_BASE + 0x038)
 #else /* defined(CONFIG_ARCH_MSM7X30) */
 #define APPS_CLK_SLEEP_EN (MSM_CSR_BASE + 0x11c)
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 6f92b27..05b574b 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/proc_comm.c
  *
  * Copyright (C) 2007-2008 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
  * Author: Brian Swetland <swetland@google.com>
  *
  * This software is licensed under the terms of the GNU General Public
@@ -31,7 +31,7 @@
 	/* Make sure the write completes before interrupt */
 	wmb();
 #if defined(CONFIG_ARCH_MSM7X30)
-	__raw_writel(1 << 6, MSM_GCC_BASE + 0x8);
+	__raw_writel(1 << 6, MSM_APCS_GCC_BASE + 0x8);
 #elif defined(CONFIG_ARCH_MSM8X60)
 	__raw_writel(1 << 5, MSM_GCC_BASE + 0x8);
 #else
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index d7f2623..c237978 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -200,13 +200,13 @@
 
 #if defined(CONFIG_ARCH_MSM7X30)
 #define MSM_TRIG_A2M_SMD_INT     \
-			(smd_write_intr(1 << 0, MSM_GCC_BASE + 0x8))
+			(smd_write_intr(1 << 0, MSM_APCS_GCC_BASE + 0x8))
 #define MSM_TRIG_A2Q6_SMD_INT    \
-			(smd_write_intr(1 << 8, MSM_GCC_BASE + 0x8))
+			(smd_write_intr(1 << 8, MSM_APCS_GCC_BASE + 0x8))
 #define MSM_TRIG_A2M_SMSM_INT    \
-			(smd_write_intr(1 << 5, MSM_GCC_BASE + 0x8))
+			(smd_write_intr(1 << 5, MSM_APCS_GCC_BASE + 0x8))
 #define MSM_TRIG_A2Q6_SMSM_INT   \
-			(smd_write_intr(1 << 8, MSM_GCC_BASE + 0x8))
+			(smd_write_intr(1 << 8, MSM_APCS_GCC_BASE + 0x8))
 #define MSM_TRIG_A2DSPS_SMD_INT
 #define MSM_TRIG_A2DSPS_SMSM_INT
 #define MSM_TRIG_A2WCNSS_SMD_INT