ASoC: wcd9304: Fix wrong sample rate issue in RX2/RX3 channels

The default value of RX2/3_B5_CTL is wrong and resulting in wrong
sample rate playback for headphone.

Change-Id: Idf7d9bce1ee344677c48353fb3fe6a8f8bcc42ab
CRs-Fixed: 361414
Signed-off-by: Asish Bhattacharya <asishb@codeaurora.org>
diff --git a/include/linux/mfd/wcd9xxx/wcd9304_registers.h b/include/linux/mfd/wcd9xxx/wcd9304_registers.h
index 70902bc..53ae67b 100644
--- a/include/linux/mfd/wcd9xxx/wcd9304_registers.h
+++ b/include/linux/mfd/wcd9xxx/wcd9304_registers.h
@@ -432,8 +432,14 @@
 
 #define SITAR_A_CDC_TX1_MUX_CTL			(0x223)
 #define SITAR_A_CDC_TX1_MUX_CTL__POR			(0x00000008)
-#define SITAR_A_CDC_TX1_CLK_FS_CTL			(0x224)
-#define SITAR_A_CDC_TX1_CLK_FS_CTL__POR			(0x00000003)
+#define SITAR_A_CDC_TX1_CLK_FS_CTL                      (0x00000224)
+#define SITAR_A_CDC_TX1_CLK_FS_CTL__POR                 (0x00000003)
+#define SITAR_A_CDC_TX2_CLK_FS_CTL                      (0x0000022C)
+#define SITAR_A_CDC_TX2_CLK_FS_CTL__POR                 (0x00000003)
+#define SITAR_A_CDC_TX3_CLK_FS_CTL                      (0x00000234)
+#define SITAR_A_CDC_TX3_CLK_FS_CTL__POR                 (0x00000003)
+#define SITAR_A_CDC_TX4_CLK_FS_CTL                      (0x0000023C)
+#define SITAR_A_CDC_TX4_CLK_FS_CTL__POR                 (0x00000003)
 #define SITAR_A_CDC_TX1_DMIC_CTL			(0x225)
 #define SITAR_A_CDC_TX1_DMIC_CTL__POR			(0x00000000)
 #define SITAR_A_CDC_TX2_MUX_CTL                 (0x22B)
@@ -479,18 +485,18 @@
 #define SITAR_A_CDC_RX3_B4_CTL__POR			 (0x00000000)
 
 #define SITAR_A_CDC_RX1_B5_CTL                  (0x000002B4)
-#define SITAR_A_CDC_RX1_B5_CTL__POR			 (0x00000060)
+#define SITAR_A_CDC_RX1_B5_CTL__POR			 (0x00000078)
 #define SITAR_A_CDC_RX2_B5_CTL                  (0x000002BC)
-#define SITAR_A_CDC_RX2_B5_CTL__POR			 (0x00000060)
+#define SITAR_A_CDC_RX2_B5_CTL__POR			 (0x00000078)
 #define SITAR_A_CDC_RX3_B5_CTL                  (0x000002C4)
-#define SITAR_A_CDC_RX3_B5_CTL__POR			 (0x00000060)
+#define SITAR_A_CDC_RX3_B5_CTL__POR			 (0x00000078)
 
 #define SITAR_A_CDC_RX1_B6_CTL                  (0x000002B5)
-#define SITAR_A_CDC_RX1_B6_CTL__POR			 (0x00000000)
+#define SITAR_A_CDC_RX1_B6_CTL__POR			 (0x00000080)
 #define SITAR_A_CDC_RX2_B6_CTL                  (0x000002BD)
-#define SITAR_A_CDC_RX2_B6_CTL__POR			 (0x00000000)
+#define SITAR_A_CDC_RX2_B6_CTL__POR			 (0x00000080)
 #define SITAR_A_CDC_RX3_B6_CTL                  (0x000002C5)
-#define SITAR_A_CDC_RX3_B6_CTL__POR			 (0x00000000)
+#define SITAR_A_CDC_RX3_B6_CTL__POR			 (0x00000080)
 
 
 #define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL			(0x2B6)
diff --git a/sound/soc/codecs/wcd9304-tables.c b/sound/soc/codecs/wcd9304-tables.c
index 823f926..252cb0e 100644
--- a/sound/soc/codecs/wcd9304-tables.c
+++ b/sound/soc/codecs/wcd9304-tables.c
@@ -590,6 +590,8 @@
 	[SITAR_A_CDC_RX1_B3_CTL] = 1,
 	[SITAR_A_CDC_RX1_B4_CTL] = 1,
 	[SITAR_A_CDC_RX1_B5_CTL] = 1,
+	[SITAR_A_CDC_RX2_B5_CTL] = 1,
+	[SITAR_A_CDC_RX3_B5_CTL] = 1,
 	[SITAR_A_CDC_RX1_B6_CTL] = 1,
 	[SITAR_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
 	[SITAR_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
diff --git a/sound/soc/codecs/wcd9304.c b/sound/soc/codecs/wcd9304.c
index ff83197..c55eac0 100644
--- a/sound/soc/codecs/wcd9304.c
+++ b/sound/soc/codecs/wcd9304.c
@@ -4402,23 +4402,20 @@
 
 static const struct sitar_reg_mask_val sitar_1_1_reg_defaults[] = {
 
-	/* Sitar 1.1 MICBIAS changes */
 	SITAR_REG_VAL(SITAR_A_MICB_1_INT_RBIAS, 0x24),
 	SITAR_REG_VAL(SITAR_A_MICB_2_INT_RBIAS, 0x24),
 
-	/* Sitar 1.1 HPH changes */
 	SITAR_REG_VAL(SITAR_A_RX_HPH_BIAS_PA, 0x57),
 	SITAR_REG_VAL(SITAR_A_RX_HPH_BIAS_LDO, 0x56),
 
-	/* Sitar 1.1 EAR PA changes */
 	SITAR_REG_VAL(SITAR_A_RX_EAR_BIAS_PA, 0xA6),
 	SITAR_REG_VAL(SITAR_A_RX_EAR_GAIN, 0x02),
 	SITAR_REG_VAL(SITAR_A_RX_EAR_VCM, 0x03),
 
-	/* Sitar 1.1 RX Changes */
 	SITAR_REG_VAL(SITAR_A_CDC_RX1_B5_CTL, 0x78),
+	SITAR_REG_VAL(SITAR_A_CDC_RX2_B5_CTL, 0x78),
+	SITAR_REG_VAL(SITAR_A_CDC_RX3_B5_CTL, 0x78),
 
-	/* Sitar 1.1 RX1 and RX2 Changes */
 	SITAR_REG_VAL(SITAR_A_CDC_RX1_B6_CTL, 0x80),
 
 	SITAR_REG_VAL(SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL, 0x1B),