commit 2f64f5a020ec5f0c95272c1ad1ddfca654eda839
author Subhash Jadavani <subhashj@codeaurora.org> Tue Dec 06 17:17:23 2011 +0530
committer Subhash Jadavani <subhashj@codeaurora.org> Sat Dec 24 15:03:12 2011 +0530
tree 89bf16f97b53a4ffb4d2b854effb5cf27d1caad6
parent 1a4cb1008d4a83c6276c330eeb57a89f1e65bfe0

msm: 8960: enable SDR104 mode (UHS-I) support for SDC3 slot

SDC3 slot can support the SDR104 bus speed mode. This change
sets the SDR104 capability for SDC3 slot.

Change-Id: I160f2e95d652da07be36b50662d54a6a45f95489
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

arch/arm/mach-msm/board-8960-storage.c

diff --git a/arch/arm/mach-msm/board-8960-storage.c b/arch/arm/mach-msm/board-8960-storage.c
index 8521717..8b43d38 100644
--- a/arch/arm/mach-msm/board-8960-storage.c
+++ b/arch/arm/mach-msm/board-8960-storage.c
@@ -211,7 +211,7 @@
 };
 
 static unsigned int sdc3_sup_clk_rates[] = {
-	400000, 24000000, 48000000, 96000000
+	400000, 24000000, 48000000, 96000000, 192000000
 };
 
 #ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
@@ -252,7 +252,7 @@
 	.xpc_cap	= 1,
 	.uhs_caps	= (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
 			MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
-			MMC_CAP_MAX_CURRENT_600)
+			MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_600),
 };
 #endif