)]}'
{
  "commit": "2f794d099da2f081de2fe19b289a3aa807f735fa",
  "tree": "9d4065219b135c17c94a532fd8b4d51e49535f72",
  "parents": [
    "32647e0c1f63eead3e84d52b3edb8bc2f1fa2dd4"
  ],
  "author": {
    "name": "Manuel Lauss",
    "email": "mano@roarinelk.homelinux.net",
    "time": "Wed Mar 25 17:49:30 2009 +0100"
  },
  "committer": {
    "name": "Ralf Baechle",
    "email": "ralf@linux-mips.org",
    "time": "Mon Mar 30 14:49:46 2009 +0200"
  },
  "message": "MIPS: Alchemy: MIPS hazard workarounds are not required.\n\nThe Alchemy manuals state:\n\n\"All pipeline hazards and dependencies are enforced by hardware interlocks\n so that any sequence of instructions is guaranteed to execute correctly.\n Therefore, it is not necessary to pad legacy MIPS hazards (such as\n load delay slots and coprocessor accesses) with NOPs.\"\n\nRun-tested on Au12x0, without any ill effects.\n\nSigned-off-by: Manuel Lauss \u003cmano@roarinelk.homelinux.net\u003e\nSigned-off-by: Ralf Baechle \u003cralf@linux-mips.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "134e1fc8f4d6d7a5eb5ae3b2d361284b23ab5e95",
      "old_mode": 33188,
      "old_path": "arch/mips/include/asm/hazards.h",
      "new_id": "a12d971db4f9c8662dcd456969f38d4a1bc48402",
      "new_mode": 33188,
      "new_path": "arch/mips/include/asm/hazards.h"
    },
    {
      "type": "modify",
      "old_id": "122c9c12e75ab8134020b00562b06f6c7d09e8b5",
      "old_mode": 33188,
      "old_path": "arch/mips/mm/tlbex.c",
      "new_id": "0615b62efd6d187533bea477c968d86e5074f0b8",
      "new_mode": 33188,
      "new_path": "arch/mips/mm/tlbex.c"
    }
  ]
}